^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Atmel AT91 AIC5 (Advanced Interrupt Controller) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 SAN People
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 ATMEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) Rick Bronson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2014 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "irq-atmel-aic-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Number of irq lines managed by AIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NR_AIC5_IRQS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT91_AIC5_SSR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AT91_AIC5_INTSEL_MSK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AT91_AIC5_SMR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AT91_AIC5_SVR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AT91_AIC5_IVR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT91_AIC5_FVR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AT91_AIC5_ISR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AT91_AIC5_IPR0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AT91_AIC5_IPR1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AT91_AIC5_IPR2 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AT91_AIC5_IPR3 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AT91_AIC5_IMR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AT91_AIC5_CISR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AT91_AIC5_IECR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AT91_AIC5_IDCR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AT91_AIC5_ICCR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AT91_AIC5_ISCR 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AT91_AIC5_EOICR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AT91_AIC5_SPU 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AT91_AIC5_DCR 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AT91_AIC5_FFER 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AT91_AIC5_FFDR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AT91_AIC5_FFSR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct irq_domain *aic5_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static asmlinkage void __exception_irq_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) aic5_handle(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!irqstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) irq_reg_writel(bgc, 0, AT91_AIC5_EOICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) handle_domain_irq(aic5_domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void aic5_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Disable interrupt on AIC5. We always take the lock of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * first irq chip as all chips share the same registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) irq_gc_lock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) gc->mask_cache &= ~d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) irq_gc_unlock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void aic5_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Enable interrupt on AIC5. We always take the lock of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * first irq chip as all chips share the same registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) irq_gc_lock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) irq_reg_writel(gc, 1, AT91_AIC5_IECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gc->mask_cache |= d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) irq_gc_unlock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int aic5_retrigger(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Enable interrupt on AIC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) irq_gc_lock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) irq_reg_writel(bgc, 1, AT91_AIC5_ISCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) irq_gc_unlock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int aic5_set_type(struct irq_data *d, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int smr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) irq_gc_lock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = aic_common_set_type(d, type, &smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) irq_gc_unlock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static u32 *smr_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void aic5_suspend(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct irq_domain_chip_generic *dgc = domain->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (smr_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < domain->revmap_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) irq_reg_writel(bgc, i, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) irq_gc_lock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (i = 0; i < dgc->irqs_per_chip; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mask = 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if ((mask & gc->mask_cache) == (mask & gc->wake_active))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (mask & gc->wake_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) irq_gc_unlock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void aic5_resume(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct irq_domain_chip_generic *dgc = domain->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) irq_gc_lock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (smr_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (i = 0; i < domain->revmap_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) irq_reg_writel(bgc, i, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) irq_reg_writel(bgc, i, AT91_AIC5_SVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) for (i = 0; i < dgc->irqs_per_chip; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mask = 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!smr_cache &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ((mask & gc->mask_cache) == (mask & gc->wake_active)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (mask & gc->mask_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) irq_gc_unlock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void aic5_pm_shutdown(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct irq_domain *domain = d->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct irq_domain_chip_generic *dgc = domain->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) irq_gc_lock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) for (i = 0; i < dgc->irqs_per_chip; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) irq_gc_unlock(bgc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define aic5_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define aic5_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define aic5_pm_shutdown NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void __init aic5_hw_init(struct irq_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Perform 8 End Of Interrupt Command to make sure AIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * will not Lock out nIRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) irq_reg_writel(gc, 0, AT91_AIC5_EOICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Spurious Interrupt ID in Spurious Vector Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * When there is no current interrupt, the IRQ Vector Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * reads the value stored in AIC_SPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* No debugging in AIC: Debug (Protect) Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) irq_reg_writel(gc, 0, AT91_AIC5_DCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Disable and clear all interrupts initially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for (i = 0; i < domain->revmap_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) irq_reg_writel(gc, i, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) irq_reg_writel(gc, i, AT91_AIC5_SVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) irq_reg_writel(gc, 1, AT91_AIC5_ICCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int aic5_irq_domain_xlate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct device_node *ctrlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) irq_hw_number_t *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned smr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!bgc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) out_hwirq, out_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) irq_gc_lock_irqsave(bgc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) aic_common_set_priority(intspec[2], &smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) irq_gc_unlock_irqrestore(bgc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct irq_domain_ops aic5_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .map = irq_map_generic_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .xlate = aic5_irq_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void __init sama5d3_aic_irq_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) aic_common_rtc_irq_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void __init sam9x60_aic_irq_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) aic_common_rtc_irq_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) aic_common_rtt_irq_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct of_device_id aic5_irq_fixups[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int __init aic5_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct device_node *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int nirqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int nchips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (nirqs > NR_AIC5_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (aic5_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) domain = aic_common_of_init(node, &aic5_irq_ops, "atmel-aic5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) nirqs, aic5_irq_fixups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (IS_ERR(domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return PTR_ERR(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) aic5_domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) nchips = aic5_domain->revmap_size / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for (i = 0; i < nchips; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) gc = irq_get_domain_generic_chip(domain, i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) gc->chip_types[0].chip.irq_mask = aic5_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) gc->chip_types[0].chip.irq_unmask = aic5_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) gc->chip_types[0].chip.irq_retrigger = aic5_retrigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) gc->chip_types[0].chip.irq_set_type = aic5_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) gc->chip_types[0].chip.irq_suspend = aic5_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) gc->chip_types[0].chip.irq_resume = aic5_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) gc->chip_types[0].chip.irq_pm_shutdown = aic5_pm_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) aic5_hw_init(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) set_handle_irq(aic5_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define NR_SAMA5D2_IRQS 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int __init sama5d2_aic5_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) smr_cache = kcalloc(DIV_ROUND_UP(NR_SAMA5D2_IRQS, 32) * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sizeof(*smr_cache), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (!smr_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return aic5_of_init(node, parent, NR_SAMA5D2_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) IRQCHIP_DECLARE(sama5d2_aic5, "atmel,sama5d2-aic", sama5d2_aic5_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define NR_SAMA5D3_IRQS 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int __init sama5d3_aic5_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return aic5_of_init(node, parent, NR_SAMA5D3_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) IRQCHIP_DECLARE(sama5d3_aic5, "atmel,sama5d3-aic", sama5d3_aic5_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define NR_SAMA5D4_IRQS 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int __init sama5d4_aic5_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return aic5_of_init(node, parent, NR_SAMA5D4_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define NR_SAM9X60_IRQS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int __init sam9x60_aic5_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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