Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Atmel AT91 AIC (Advanced Interrupt Controller) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2004 SAN People
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2004 ATMEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) Rick Bronson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2014 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "irq-atmel-aic-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Number of irq lines managed by AIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define NR_AIC_IRQS	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AT91_AIC_SMR(n)			((n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AT91_AIC_SVR(n)			(0x80 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AT91_AIC_IVR			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AT91_AIC_FVR			0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AT91_AIC_ISR			0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AT91_AIC_IPR			0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AT91_AIC_IMR			0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AT91_AIC_CISR			0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AT91_AIC_IECR			0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AT91_AIC_IDCR			0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AT91_AIC_ICCR			0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AT91_AIC_ISCR			0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AT91_AIC_EOICR			0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AT91_AIC_SPU			0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define AT91_AIC_DCR			0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static struct irq_domain *aic_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static asmlinkage void __exception_irq_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) aic_handle(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct irq_domain_chip_generic *dgc = aic_domain->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct irq_chip_generic *gc = dgc->gc[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	irqnr = irq_reg_readl(gc, AT91_AIC_IVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	irqstat = irq_reg_readl(gc, AT91_AIC_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (!irqstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		irq_reg_writel(gc, 0, AT91_AIC_EOICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		handle_domain_irq(aic_domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int aic_retrigger(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* Enable interrupt on AIC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	irq_reg_writel(gc, d->mask, AT91_AIC_ISCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int aic_set_type(struct irq_data *d, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned int smr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	ret = aic_common_set_type(d, type, &smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void aic_suspend(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void aic_resume(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void aic_pm_shutdown(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define aic_suspend		NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define aic_resume		NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define aic_pm_shutdown		NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void __init aic_hw_init(struct irq_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * Perform 8 End Of Interrupt Command to make sure AIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * will not Lock out nIRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		irq_reg_writel(gc, 0, AT91_AIC_EOICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * Spurious Interrupt ID in Spurious Vector Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * When there is no current interrupt, the IRQ Vector Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * reads the value stored in AIC_SPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* No debugging in AIC: Debug (Protect) Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	irq_reg_writel(gc, 0, AT91_AIC_DCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* Disable and clear all interrupts initially */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	for (i = 0; i < 32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		irq_reg_writel(gc, i, AT91_AIC_SVR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int aic_irq_domain_xlate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				struct device_node *ctrlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				irq_hw_number_t *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct irq_domain_chip_generic *dgc = d->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned smr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (!dgc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ret = aic_common_irq_domain_xlate(d, ctrlr, intspec, intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					  out_hwirq, out_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	idx = intspec[0] / dgc->irqs_per_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (idx >= dgc->num_chips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	gc = dgc->gc[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	irq_gc_lock_irqsave(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	aic_common_set_priority(intspec[2], &smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	irq_gc_unlock_irqrestore(gc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct irq_domain_ops aic_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.map	= irq_map_generic_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.xlate	= aic_irq_domain_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void __init at91rm9200_aic_irq_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	aic_common_rtc_irq_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void __init at91sam9260_aic_irq_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	aic_common_rtt_irq_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void __init at91sam9g45_aic_irq_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	aic_common_rtc_irq_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	aic_common_rtt_irq_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct of_device_id aic_irq_fixups[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	{ .compatible = "atmel,at91rm9200", .data = at91rm9200_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	{ .compatible = "atmel,at91sam9g45", .data = at91sam9g45_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	{ .compatible = "atmel,at91sam9n12", .data = at91rm9200_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{ .compatible = "atmel,at91sam9rl", .data = at91sam9g45_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{ .compatible = "atmel,at91sam9x5", .data = at91rm9200_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{ .compatible = "atmel,at91sam9260", .data = at91sam9260_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	{ .compatible = "atmel,at91sam9261", .data = at91sam9260_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	{ .compatible = "atmel,at91sam9263", .data = at91sam9260_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	{ .compatible = "atmel,at91sam9g20", .data = at91sam9260_aic_irq_fixup },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int __init aic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			      struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (aic_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	domain = aic_common_of_init(node, &aic_irq_ops, "atmel-aic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 				    NR_AIC_IRQS, aic_irq_fixups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (IS_ERR(domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return PTR_ERR(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	aic_domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	gc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	gc->chip_types[0].regs.enable = AT91_AIC_IECR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	gc->chip_types[0].regs.disable = AT91_AIC_IDCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	gc->chip_types[0].chip.irq_retrigger = aic_retrigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	gc->chip_types[0].chip.irq_set_type = aic_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	gc->chip_types[0].chip.irq_suspend = aic_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	gc->chip_types[0].chip.irq_resume = aic_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	aic_hw_init(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	set_handle_irq(aic_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IRQCHIP_DECLARE(at91rm9200_aic, "atmel,at91rm9200-aic", aic_of_init);