^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Atmel AT91 common AIC (Advanced Interrupt Controller) code shared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * irq-atmel-aic and irq-atmel-aic5 drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 SAN People
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 ATMEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) Rick Bronson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2014 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "irq-atmel-aic-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AT91_AIC_PRIOR GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AT91_AIC_IRQ_MIN_PRIORITY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AT91_AIC_IRQ_MAX_PRIORITY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AT91_AIC_SRCTYPE GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AT91_AIC_SRCTYPE_LOW (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AT91_AIC_SRCTYPE_FALLING (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AT91_AIC_SRCTYPE_HIGH (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AT91_AIC_SRCTYPE_RISING (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct aic_chip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 ext_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void aic_common_shutdown(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ct->chip.irq_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct aic_chip_data *aic = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned aic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) aic_type = AT91_AIC_SRCTYPE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) aic_type = AT91_AIC_SRCTYPE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (!(d->mask & aic->ext_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) aic_type = AT91_AIC_SRCTYPE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (!(d->mask & aic->ext_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) aic_type = AT91_AIC_SRCTYPE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *val &= ~AT91_AIC_SRCTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *val |= aic_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void aic_common_set_priority(int priority, unsigned *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *val &= ~AT91_AIC_PRIOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *val |= priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int aic_common_irq_domain_xlate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct device_node *ctrlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const u32 *intspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) irq_hw_number_t *out_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int *out_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (WARN_ON(intsize < 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *out_hwirq = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct device_node *node = irq_domain_get_of_node(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct aic_chip_data *aic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) gc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) aic = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) aic->ext_irqs |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) of_property_for_each_u32(node, "atmel,external-irqs", prop, p, hwirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) gc = irq_get_domain_generic_chip(domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!gc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pr_warn("AIC: external irq %d >= %d skip it\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) hwirq, domain->revmap_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) aic = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) aic->ext_irqs |= (1 << (hwirq % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AT91_RTC_IDR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AT91_RTC_IMR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AT91_RTC_IRQ_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void __init aic_common_rtc_irq_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "atmel,at91sam9x5-rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regs = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writel(AT91_RTC_IRQ_MASK, regs + AT91_RTC_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AT91_RTT_MR 0x00 /* Real-time Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __init aic_common_rtt_irq_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * The at91sam9263 SoC has 2 instances of the RTT block, hence we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * iterate over the DT to find each occurrence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for_each_compatible_node(np, NULL, "atmel,at91sam9260-rtt") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) regs = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel(readl(regs + AT91_RTT_MR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) regs + AT91_RTT_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void __init aic_common_irq_fixup(const struct of_device_id *matches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct device_node *root = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) match = of_match_node(matches, root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void (*fixup)(void) = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) of_node_put(root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct irq_domain *__init aic_common_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const struct irq_domain_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const char *name, int nirqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const struct of_device_id *matches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct aic_chip_data *aic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int nchips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) nchips = DIV_ROUND_UP(nirqs, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) reg_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) aic = kcalloc(nchips, sizeof(*aic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!aic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) domain = irq_domain_add_linear(node, nchips * 32, ops, aic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) goto err_free_aic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = irq_alloc_domain_generic_chips(domain, 32, 1, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) handle_fasteoi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IRQ_NOREQUEST | IRQ_NOPROBE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IRQ_NOAUTOEN, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) goto err_domain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 0; i < nchips; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) gc = irq_get_domain_generic_chip(domain, i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) gc->reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) gc->unused = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) gc->wake_enabled = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) gc->chip_types[0].chip.irq_eoi = irq_gc_eoi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) gc->private = &aic[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) aic_common_ext_irq_of_init(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) aic_common_irq_fixup(matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) err_domain_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err_free_aic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) kfree(aic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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