^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for Aspeed "new" VIC as found in SoC generation 3 and later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on irq-vic.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999 - 2003 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2000 Deep Blue Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* These definitions correspond to the "new mapping" of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * register set that interleaves "high" and "low". The offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * below are for the "low" register, add 4 to get to the high one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AVIC_IRQ_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AVIC_FIQ_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AVIC_RAW_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AVIC_INT_SELECT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AVIC_INT_ENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AVIC_INT_ENABLE_CLR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AVIC_INT_TRIGGER 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AVIC_INT_TRIGGER_CLR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AVIC_INT_SENSE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AVIC_INT_DUAL_EDGE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AVIC_INT_EVENT 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AVIC_EDGE_CLR 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AVIC_EDGE_STATUS 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NUM_IRQS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct aspeed_vic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 edge_sources[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct irq_domain *dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct aspeed_vic *system_avic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void vic_init_hw(struct aspeed_vic *vic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Make sure no soft trigger is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Set everything to be IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(0, vic->base + AVIC_INT_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel(0, vic->base + AVIC_INT_SELECT + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Some interrupts have a programable high/low level trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * (4 GPIO direct inputs), for now we assume this was configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * by firmware. We read which ones are edge now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) sense = readl(vic->base + AVIC_INT_SENSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) vic->edge_sources[0] = ~sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) sense = readl(vic->base + AVIC_INT_SENSE + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) vic->edge_sources[1] = ~sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Clear edge detection latches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel(0xffffffff, vic->base + AVIC_EDGE_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct aspeed_vic *vic = system_avic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 stat, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) irq = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (stat == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) irq += ffs(stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) handle_domain_irq(vic->dom, irq, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void avic_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int sidx = d->hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int sbit = 1u << (d->hwirq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Clear edge latch for edge interrupts, nop for level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (vic->edge_sources[sidx] & sbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void avic_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int sidx = d->hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int sbit = 1u << (d->hwirq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void avic_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int sidx = d->hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int sbit = 1u << (d->hwirq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* For level irq, faster than going through a nop "ack" and mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void avic_mask_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int sidx = d->hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int sbit = 1u << (d->hwirq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* First mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Then clear edge latch for edge interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (vic->edge_sources[sidx] & sbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct irq_chip avic_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .name = "AVIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .irq_ack = avic_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .irq_mask = avic_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .irq_unmask = avic_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .irq_mask_ack = avic_mask_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int avic_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct aspeed_vic *vic = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int sidx = hwirq >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int sbit = 1u << (hwirq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Check if interrupt exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (sidx > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (vic->edge_sources[sidx] & sbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) irq_set_chip_data(irq, vic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq_set_probe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct irq_domain_ops avic_dom_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .map = avic_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int __init avic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct aspeed_vic *vic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (WARN(parent, "non-root Aspeed VIC not supported"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (WARN(system_avic, "duplicate Aspeed VIC not supported"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) regs = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (WARN_ON(!regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (WARN_ON(!vic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) vic->base = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Initialize soures, all masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) vic_init_hw(vic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Ready to receive interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) system_avic = vic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) set_handle_irq(avic_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Register our domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) &avic_dom_ops, vic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IRQCHIP_DECLARE(ast2400_vic, "aspeed,ast2400-vic", avic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) IRQCHIP_DECLARE(ast2500_vic, "aspeed,ast2500-vic", avic_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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