^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2019 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Eddie James <eajames@linux.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ASPEED_SCU_IC_REG 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ASPEED_SCU_IC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ASPEED_SCU_IC_ENABLE GENMASK(6, ASPEED_SCU_IC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ASPEED_SCU_IC_NUM_IRQS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ASPEED_SCU_IC_STATUS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ASPEED_AST2600_SCU_IC0_REG 0x560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ASPEED_AST2600_SCU_IC0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ASPEED_AST2600_SCU_IC0_ENABLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) GENMASK(5, ASPEED_AST2600_SCU_IC0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ASPEED_AST2600_SCU_IC0_NUM_IRQS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ASPEED_AST2600_SCU_IC1_REG 0x570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ASPEED_AST2600_SCU_IC1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ASPEED_AST2600_SCU_IC1_ENABLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) GENMASK(5, ASPEED_AST2600_SCU_IC1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ASPEED_AST2600_SCU_IC1_NUM_IRQS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct aspeed_scu_ic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long irq_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap *scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void aspeed_scu_ic_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * The SCU IC has just one register to control its operation and read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * status. The interrupt enable bits occupy the lower 16 bits of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * register, while the interrupt status bits occupy the upper 16 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * The status bit for a given interrupt is always 16 bits shifted from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * the enable bit for the same interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Therefore, perform the IRQ operations in the enable bit space by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * shifting the status down to get the mapping and then back up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * clear the bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_read(scu_ic->scu, scu_ic->reg, &sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enabled = sts & scu_ic->irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) status = (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bit = scu_ic->irq_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) max = scu_ic->num_irqs + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for_each_set_bit_from(bit, &status, max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) irq = irq_find_mapping(scu_ic->irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bit - scu_ic->irq_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regmap_write_bits(scu_ic->scu, scu_ic->reg, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void aspeed_scu_ic_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Status bits are cleared by writing 1. In order to prevent the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * operation from clearing the status bits, they should be under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * mask and written with 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void aspeed_scu_ic_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int mask = bit |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Status bits are cleared by writing 1. In order to prevent the unmask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * operation from clearing the status bits, they should be under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * mask and written with 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const struct cpumask *dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct irq_chip aspeed_scu_ic_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = "aspeed-scu-ic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .irq_mask = aspeed_scu_ic_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .irq_unmask = aspeed_scu_ic_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .irq_set_affinity = aspeed_scu_ic_irq_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int aspeed_scu_ic_map(struct irq_domain *domain, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) irq_set_chip_data(irq, domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct irq_domain_ops aspeed_scu_ic_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .map = aspeed_scu_ic_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!node->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) scu_ic->scu = syscon_node_to_regmap(node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (IS_ERR(scu_ic->scu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rc = PTR_ERR(scu_ic->scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rc = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) scu_ic->irq_domain = irq_domain_add_linear(node, scu_ic->num_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) &aspeed_scu_ic_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) scu_ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!scu_ic->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) scu_ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) kfree(scu_ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int __init aspeed_scu_ic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!scu_ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) scu_ic->irq_enable = ASPEED_SCU_IC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) scu_ic->irq_shift = ASPEED_SCU_IC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) scu_ic->num_irqs = ASPEED_SCU_IC_NUM_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) scu_ic->reg = ASPEED_SCU_IC_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return aspeed_scu_ic_of_init_common(scu_ic, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int __init aspeed_ast2600_scu_ic0_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!scu_ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) scu_ic->irq_enable = ASPEED_AST2600_SCU_IC0_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) scu_ic->irq_shift = ASPEED_AST2600_SCU_IC0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) scu_ic->num_irqs = ASPEED_AST2600_SCU_IC0_NUM_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) scu_ic->reg = ASPEED_AST2600_SCU_IC0_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return aspeed_scu_ic_of_init_common(scu_ic, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int __init aspeed_ast2600_scu_ic1_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!scu_ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) scu_ic->irq_enable = ASPEED_AST2600_SCU_IC1_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) scu_ic->irq_shift = ASPEED_AST2600_SCU_IC1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) scu_ic->num_irqs = ASPEED_AST2600_SCU_IC1_NUM_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) scu_ic->reg = ASPEED_AST2600_SCU_IC1_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return aspeed_scu_ic_of_init_common(scu_ic, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) aspeed_ast2600_scu_ic0_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) aspeed_ast2600_scu_ic1_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags