^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Aspeed 24XX/25XX I2C Interrupt Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012-2017 ASPEED Technology Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2017 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2017 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ASPEED_I2C_IC_NUM_BUS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct aspeed_i2c_ic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * The aspeed chip provides a single hardware interrupt for all of the I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * busses, so we use a dummy interrupt chip to translate this single interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * into multiple interrupts, each associated with a single I2C bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void aspeed_i2c_ic_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct aspeed_i2c_ic *i2c_ic = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long bit, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int bus_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) status = readl(i2c_ic->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for_each_set_bit(bit, &status, ASPEED_I2C_IC_NUM_BUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) bus_irq = irq_find_mapping(i2c_ic->irq_domain, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) generic_handle_irq(bus_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Set simple handler and mark IRQ as valid. Nothing interesting to do here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * since we are using a dummy interrupt chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int aspeed_i2c_ic_map_irq_domain(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int irq, irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) irq_set_chip_data(irq, domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct irq_domain_ops aspeed_i2c_ic_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .map = aspeed_i2c_ic_map_irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int __init aspeed_i2c_ic_of_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct aspeed_i2c_ic *i2c_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) i2c_ic = kzalloc(sizeof(*i2c_ic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!i2c_ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) i2c_ic->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!i2c_ic->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) goto err_free_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) i2c_ic->parent_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (i2c_ic->parent_irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = i2c_ic->parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) i2c_ic->irq_domain = irq_domain_add_linear(node, ASPEED_I2C_IC_NUM_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) &aspeed_i2c_ic_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!i2c_ic->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) i2c_ic->irq_domain->name = "aspeed-i2c-domain";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) irq_set_chained_handler_and_data(i2c_ic->parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) aspeed_i2c_ic_irq_handler, i2c_ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pr_info("i2c controller registered, irq %d\n", i2c_ic->parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) iounmap(i2c_ic->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) err_free_ic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) kfree(i2c_ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) IRQCHIP_DECLARE(ast2400_i2c_ic, "aspeed,ast2400-i2c-ic", aspeed_i2c_ic_of_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) IRQCHIP_DECLARE(ast2500_i2c_ic, "aspeed,ast2500-i2c-ic", aspeed_i2c_ic_of_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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