Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Annapurna Labs MSIX support services
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2016, Amazon.com, Inc. or its affiliates. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Antoine Tenart <antoine.tenart@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* MSIX message address format: local GIC target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ALPINE_MSIX_SPI_TARGET_CLUSTER0		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct alpine_msix_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	spinlock_t msi_map_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	phys_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 spi_first;		/* The SGI number that MSIs start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 num_spis;		/* The number of SGIs for MSIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	unsigned long *msi_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static void alpine_msix_mask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	pci_msi_mask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void alpine_msix_unmask_msi_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	pci_msi_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct irq_chip alpine_msix_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.name			= "MSIx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.irq_mask		= alpine_msix_mask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.irq_unmask		= alpine_msix_unmask_msi_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.irq_eoi		= irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.irq_set_affinity	= irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int alpine_msix_allocate_sgi(struct alpine_msix_data *priv, int num_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	int first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	spin_lock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 					   num_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (first >= priv->num_spis) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		spin_unlock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	bitmap_set(priv->msi_map, first, num_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	spin_unlock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return priv->spi_first + first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void alpine_msix_free_sgi(struct alpine_msix_data *priv, unsigned sgi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				 int num_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int first = sgi - priv->spi_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	spin_lock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	bitmap_clear(priv->msi_map, first, num_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	spin_unlock(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void alpine_msix_compose_msi_msg(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 					struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct alpine_msix_data *priv = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	phys_addr_t msg_addr = priv->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	msg_addr |= (data->hwirq << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	msg->address_hi = upper_32_bits(msg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	msg->address_lo = lower_32_bits(msg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	msg->data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct msi_domain_info alpine_msix_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.flags	= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		  MSI_FLAG_PCI_MSIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.chip	= &alpine_msix_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct irq_chip middle_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.name			= "alpine_msix_middle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.irq_mask		= irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.irq_unmask		= irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.irq_eoi		= irq_chip_eoi_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.irq_set_affinity	= irq_chip_set_affinity_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.irq_compose_msi_msg	= alpine_msix_compose_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int alpine_msix_gic_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 					unsigned int virq, int sgi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct irq_data *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (!is_of_node(domain->parent->fwnode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	fwspec.fwnode = domain->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	fwspec.param_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	fwspec.param[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	fwspec.param[1] = sgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	d = irq_domain_get_irq_data(domain->parent, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int alpine_msix_middle_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 					   unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					   unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct alpine_msix_data *priv = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int sgi, err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	sgi = alpine_msix_allocate_sgi(priv, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (sgi < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return sgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		err = alpine_msix_gic_domain_alloc(domain, virq + i, sgi + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			goto err_sgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		irq_domain_set_hwirq_and_chip(domain, virq + i, sgi + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					      &middle_irq_chip, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err_sgi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	irq_domain_free_irqs_parent(domain, virq, i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	alpine_msix_free_sgi(priv, sgi, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void alpine_msix_middle_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 					   unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 					   unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct alpine_msix_data *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	alpine_msix_free_sgi(priv, d->hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct irq_domain_ops alpine_msix_middle_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.alloc	= alpine_msix_middle_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.free	= alpine_msix_middle_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int alpine_msix_init_domains(struct alpine_msix_data *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				    struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct irq_domain *middle_domain, *msi_domain, *gic_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct device_node *gic_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	gic_node = of_irq_find_parent(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (!gic_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		pr_err("Failed to find the GIC node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	gic_domain = irq_find_host(gic_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (!gic_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		pr_err("Failed to find the GIC domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	middle_domain = irq_domain_add_tree(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					    &alpine_msix_middle_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 					    priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (!middle_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		pr_err("Failed to create the MSIX middle domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	middle_domain->parent = gic_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 					       &alpine_msix_domain_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 					       middle_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		pr_err("Failed to create MSI domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		irq_domain_remove(middle_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int alpine_msix_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			    struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct alpine_msix_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	spin_lock_init(&priv->msi_map_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	ret = of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		pr_err("Failed to allocate resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * The 20 least significant bits of addr provide direct information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 * regarding the interrupt destination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 * To select the primary GIC as the target GIC, bits [18:17] must be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 * to 0x0. In this case, bit 16 (SPI_TARGET_CLUSTER0) must be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	priv->addr = res.start & GENMASK_ULL(63,20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	priv->addr |= ALPINE_MSIX_SPI_TARGET_CLUSTER0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (of_property_read_u32(node, "al,msi-base-spi", &priv->spi_first)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		pr_err("Unable to parse MSI base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (of_property_read_u32(node, "al,msi-num-spis", &priv->num_spis)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		pr_err("Unable to parse MSI numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	priv->msi_map = kcalloc(BITS_TO_LONGS(priv->num_spis),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				sizeof(*priv->msi_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (!priv->msi_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		goto err_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	pr_debug("Registering %d msixs, starting at %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		 priv->num_spis, priv->spi_first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	ret = alpine_msix_init_domains(priv, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		goto err_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) err_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	kfree(priv->msi_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) err_priv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) IRQCHIP_DECLARE(alpine_msix, "al,alpine-msix", alpine_msix_init);