^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* FIC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AL_FIC_CAUSE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AL_FIC_SET_CAUSE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AL_FIC_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AL_FIC_CONTROL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CONTROL_TRIGGER_RISING BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CONTROL_MASK_MSI_X BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NR_FIC_IRQS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_AUTHOR("Talel Shenhar");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum al_fic_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) AL_FIC_UNCONFIGURED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) AL_FIC_CONFIGURED_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) AL_FIC_CONFIGURED_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct al_fic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum al_fic_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void al_fic_set_trigger(struct al_fic *fic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct irq_chip_generic *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum al_fic_state new_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) irq_flow_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (new_state == AL_FIC_CONFIGURED_LEVEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) control &= ~CONTROL_TRIGGER_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) control |= CONTROL_TRIGGER_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) gc->chip_types->handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) fic->state = new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel_relaxed(control, fic->base + AL_FIC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int al_fic_irq_set_type(struct irq_data *data, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct al_fic *fic = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum al_fic_state new_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) irq_gc_lock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pr_debug("fic doesn't support flow type %d\n", flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) new_state = (flow_type & IRQ_TYPE_LEVEL_HIGH) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) AL_FIC_CONFIGURED_LEVEL : AL_FIC_CONFIGURED_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * A given FIC instance can be either all level or all edge triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * This is generally fixed depending on what pieces of HW it's wired up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * We configure it based on the sensitivity of the first source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * being setup, and reject any subsequent attempt at configuring it in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * different way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (fic->state == AL_FIC_UNCONFIGURED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) al_fic_set_trigger(fic, gc, new_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } else if (fic->state != new_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pr_debug("fic %s state already configured to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) fic->name, fic->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) irq_gc_unlock(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void al_fic_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct al_fic *fic = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct irq_domain *domain = fic->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pending = readl_relaxed(fic->base + AL_FIC_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pending &= ~gc->mask_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for_each_set_bit(hwirq, &pending, NR_FIC_IRQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) irq = irq_find_mapping(domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int al_fic_irq_retrigger(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct al_fic *fic = gc->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int al_fic_register(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct al_fic *fic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) fic->domain = irq_domain_add_linear(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) NR_FIC_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &irq_generic_chip_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) fic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!fic->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pr_err("fail to add irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = irq_alloc_domain_generic_chips(fic->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) NR_FIC_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 1, fic->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) handle_level_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0, 0, IRQ_GC_INIT_MASK_CACHE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_err("fail to allocate generic chip (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto err_domain_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) gc = irq_get_domain_generic_chip(fic->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) gc->reg_base = fic->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) gc->chip_types->regs.mask = AL_FIC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) gc->chip_types->regs.ack = AL_FIC_CAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) gc->chip_types->chip.irq_set_type = al_fic_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) gc->private = fic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) irq_set_chained_handler_and_data(fic->parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) al_fic_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) fic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) err_domain_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) irq_domain_remove(fic->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * al_fic_wire_init() - initialize and configure fic in wire mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @of_node: optional pointer to interrupt controller's device tree node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @base: mmio to fic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @name: name of the fic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @parent_irq: interrupt of parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * This API will configure the fic hardware to to work in wire mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * In wire mode, fic hardware is generating a wire ("wired") interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Interrupt can be generated based on positive edge or level - configuration is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * to be determined based on connected hardware to this fic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct al_fic *al_fic_wire_init(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int parent_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct al_fic *fic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 control = CONTROL_MASK_MSI_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) fic = kzalloc(sizeof(*fic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!fic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) fic->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) fic->parent_irq = parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) fic->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* mask out all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* clear any pending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel_relaxed(0, fic->base + AL_FIC_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel_relaxed(control, fic->base + AL_FIC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = al_fic_register(node, fic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pr_err("fail to register irqchip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pr_debug("%s initialized successfully in Legacy mode (parent-irq=%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) fic->name, parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return fic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) kfree(fic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int __init al_fic_init_dt(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct al_fic *fic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_err("%s: unsupported - device require a parent\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_err("%s: fail to map memory\n", node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) parent_irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!parent_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pr_err("%s: fail to map irq\n", node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) fic = al_fic_wire_init(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) node->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (IS_ERR(fic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pr_err("%s: fail to initialize irqchip (%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) node->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PTR_ERR(fic));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = PTR_ERR(fic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto err_irq_dispose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) err_irq_dispose:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) irq_dispose_mapping(parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) IRQCHIP_DECLARE(al_fic, "amazon,al-fic", al_fic_init_dt);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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