^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _ALPHASCALE_ASM9260_ICOLL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _ALPHASCALE_ASM9260_ICOLL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ASM9260_NUM_IRQS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * this device provide 4 offsets for each register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 0x0 - plain read write mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 0x4 - set mode, OR logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 0x8 - clr mode, XOR logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 0xc - togle mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ASM9260_HW_ICOLL_VECTOR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * bits 31:2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * This register presents the vector address for the interrupt currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * active on the CPU IRQ input. Writing to this register notifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * interrupt collector that the interrupt service routine for the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * interrupt has been entered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * The exception trap should have a LDPC instruction from this address:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * LDPC ASM9260_HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The Interrupt Collector Level Acknowledge Register is used by software to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * indicate the completion of an interrupt on a specific level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This register is written at the very end of an interrupt service routine. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * nesting is used then the CPU irq must be turned on before writing to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * register to avoid a race condition in the CPU interrupt hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ASM9260_HW_ICOLL_LEVELACK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ASM9260_BM_LEVELn(nr) BIT(nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ASM9260_HW_ICOLL_CTRL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * ASM9260_BM_CTRL_SFTRST and ASM9260_BM_CTRL_CLKGATE are not available on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * asm9260.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ASM9260_BM_CTRL_SFTRST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ASM9260_BM_CTRL_CLKGATE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* disable interrupt level nesting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ASM9260_BM_CTRL_NO_NESTING BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Set this bit to one enable the RISC32-style read side effect associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * the vector address register. In this mode, interrupt in-service is signaled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * by the read of the ASM9260_HW_ICOLL_VECTOR register to acquire the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * vector address. Set this bit to zero for normal operation, in which the ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * signals in-service explicitly by means of a write to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * ASM9260_HW_ICOLL_VECTOR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 0 - Must Write to Vector register to go in-service.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 1 - Go in-service as a read side effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ASM9260_BM_CTRL_ARM_RSE_MODE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ASM9260_BM_CTRL_IRQ_ENABLE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ASM9260_HW_ICOLL_STAT_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * bits 5:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Vector number of current interrupt. Multiply by 4 and add to vector base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * address to obtain the value in ASM9260_HW_ICOLL_VECTOR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * RAW0 and RAW1 provides a read-only view of the raw interrupt request lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * coming from various parts of the chip. Its purpose is to improve diagnostic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * observability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ASM9260_HW_ICOLL_RAW0 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ASM9260_HW_ICOLL_RAW1 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ASM9260_HW_ICOLL_INTERRUPT0 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ASM9260_HW_ICOLL_INTERRUPTn(n) (0x0060 + ((n) >> 2) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * WARNING: Modifying the priority of an enabled interrupt may result in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * undefined behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ASM9260_BM_INT_PRIORITY_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ASM9260_BM_INT_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ASM9260_BM_INT_SOFTIRQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n) (((n) & 0x3) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ASM9260_BM_ICOLL_INTERRUPTn_ENABLE(n) (1 << (2 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ASM9260_HW_ICOLL_VBASE 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * bits 31:2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * This bitfield holds the upper 30 bits of the base address of the vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ASM9260_HW_ICOLL_CLEAR0 0x01d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ASM9260_HW_ICOLL_CLEAR1 0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ASM9260_HW_ICOLL_CLEARn(n) (((n >> 5) * 0x10) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) + SET_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ASM9260_BM_CLEAR_BIT(n) BIT(n & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Scratchpad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ASM9260_HW_ICOLL_UNDEF_VECTOR 0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags