Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * scc2698.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * driver for the IPOCTAL boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2009-2012 CERN (www.cern.ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Nicolas Serafini, EIC2 SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef SCC2698_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define SCC2698_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * union scc2698_channel - Channel access to scc2698 IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * dn value are only spacer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) union scc2698_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		u8 d0, mr;  /* Mode register 1/2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		u8 d1, sr;  /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		u8 d2, r1;  /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		u8 d3, rhr; /* Receive holding register (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		u8 junk[8]; /* other crap for block control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	} __packed r; /* Read access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		u8 d0, mr;  /* Mode register 1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		u8 d1, csr; /* Clock select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		u8 d2, cr;  /* Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		u8 d3, thr; /* Transmit holding register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		u8 junk[8]; /* other crap for block control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	} __packed w; /* Write access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * union scc2698_block - Block access to scc2698 IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * The scc2698 contain 4 block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * Each block containt two channel a and b.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * dn value are only spacer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) union scc2698_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		u8 d0, mra;  /* Mode register 1/2 (a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		u8 d1, sra;  /* Status register (a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		u8 d2, r1;   /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		u8 d3, rhra; /* Receive holding register (a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		u8 d4, ipcr; /* Input port change register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		u8 d5, isr;  /* Interrupt status register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		u8 d6, ctur; /* Counter timer upper register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		u8 d7, ctlr; /* Counter timer lower register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		u8 d8, mrb;  /* Mode register 1/2 (b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		u8 d9, srb;  /* Status register (b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		u8 da, r2;   /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		u8 db, rhrb; /* Receive holding register (b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		u8 dc, r3;   /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		u8 dd, ip;   /* Input port register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		u8 de, ctg;  /* Start counter timer of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		u8 df, cts;  /* Stop counter timer of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	} __packed r; /* Read access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		u8 d0, mra;  /* Mode register 1/2 (a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		u8 d1, csra; /* Clock select register (a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		u8 d2, cra;  /* Command register (a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		u8 d3, thra; /* Transmit holding register (a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		u8 d4, acr;  /* Auxiliary control register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		u8 d5, imr;  /* Interrupt mask register of block  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		u8 d6, ctu;  /* Counter timer upper register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		u8 d7, ctl;  /* Counter timer lower register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		u8 d8, mrb;  /* Mode register 1/2 (b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		u8 d9, csrb; /* Clock select register (a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		u8 da, crb;  /* Command register (b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		u8 db, thrb; /* Transmit holding register (b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		u8 dc, r1;   /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		u8 dd, opcr; /* Output port configuration register of block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		u8 de, r2;   /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		u8 df, r3;   /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	} __packed w; /* Write access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MR1_CHRL_5_BITS             (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MR1_CHRL_6_BITS             (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MR1_CHRL_7_BITS             (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MR1_CHRL_8_BITS             (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MR1_PARITY_EVEN             (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MR1_PARITY_ODD              (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MR1_PARITY_ON               (0x0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MR1_PARITY_FORCE            (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define MR1_PARITY_OFF              (0x2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MR1_PARITY_SPECIAL          (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MR1_ERROR_CHAR              (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MR1_ERROR_BLOCK             (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MR1_RxINT_RxRDY             (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MR1_RxINT_FFULL             (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MR1_RxRTS_CONTROL_ON        (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MR1_RxRTS_CONTROL_OFF       (0x0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MR2_STOP_BITS_LENGTH_1      (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MR2_STOP_BITS_LENGTH_2      (0xF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MR2_CTS_ENABLE_TX_ON        (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MR2_CTS_ENABLE_TX_OFF       (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MR2_TxRTS_CONTROL_ON        (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MR2_TxRTS_CONTROL_OFF       (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MR2_CH_MODE_NORMAL          (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MR2_CH_MODE_ECHO            (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MR2_CH_MODE_LOCAL           (0x2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MR2_CH_MODE_REMOTE          (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CR_ENABLE_RX                (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CR_DISABLE_RX               (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CR_ENABLE_TX                (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CR_DISABLE_TX               (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CR_CMD_RESET_MR             (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CR_CMD_RESET_RX             (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CR_CMD_RESET_TX             (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CR_CMD_RESET_ERR_STATUS     (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CR_CMD_RESET_BREAK_CHANGE   (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CR_CMD_START_BREAK          (0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CR_CMD_STOP_BREAK           (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CR_CMD_ASSERT_RTSN          (0x8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CR_CMD_NEGATE_RTSN          (0x9 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CR_CMD_SET_TIMEOUT_MODE     (0xA << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CR_CMD_DISABLE_TIMEOUT_MODE (0xC << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SR_RX_READY                 (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SR_FIFO_FULL                (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SR_TX_READY                 (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SR_TX_EMPTY                 (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SR_OVERRUN_ERROR            (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SR_PARITY_ERROR             (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SR_FRAMING_ERROR            (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SR_RECEIVED_BREAK           (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SR_ERROR                    (0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ACR_DELTA_IP0_IRQ_EN        (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ACR_DELTA_IP1_IRQ_EN        (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ACR_DELTA_IP2_IRQ_EN        (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ACR_DELTA_IP3_IRQ_EN        (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ACR_CT_Mask                 (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ACR_CExt                    (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ACR_CTxCA                   (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ACR_CTxCB                   (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ACR_CClk16                  (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ACR_TExt                    (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ACR_TExt16                  (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ACR_TClk                    (0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ACR_TClk16                  (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ACR_BRG_SET1                (0x0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ACR_BRG_SET2                (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TX_CLK_75                   (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TX_CLK_110                  (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TX_CLK_38400                (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TX_CLK_150                  (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TX_CLK_300                  (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TX_CLK_600                  (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TX_CLK_1200                 (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TX_CLK_2000                 (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TX_CLK_2400                 (0x8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TX_CLK_4800                 (0x9 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TX_CLK_1800                 (0xA << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TX_CLK_9600                 (0xB << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TX_CLK_19200                (0xC << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RX_CLK_75                   (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RX_CLK_110                  (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RX_CLK_38400                (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RX_CLK_150                  (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RX_CLK_300                  (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RX_CLK_600                  (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RX_CLK_1200                 (0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RX_CLK_2000                 (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RX_CLK_2400                 (0x8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RX_CLK_4800                 (0x9 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RX_CLK_1800                 (0xA << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RX_CLK_9600                 (0xB << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RX_CLK_19200                (0xC << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OPCR_MPOa_RTSN              (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OPCR_MPOa_C_TO              (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OPCR_MPOa_TxC1X             (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OPCR_MPOa_TxC16X            (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OPCR_MPOa_RxC1X             (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OPCR_MPOa_RxC16X            (0x5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OPCR_MPOa_TxRDY             (0x6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OPCR_MPOa_RxRDY_FF          (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OPCR_MPOb_RTSN              (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OPCR_MPOb_C_TO              (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OPCR_MPOb_TxC1X             (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OPCR_MPOb_TxC16X            (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OPCR_MPOb_RxC1X             (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OPCR_MPOb_RxC16X            (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OPCR_MPOb_TxRDY             (0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OPCR_MPOb_RxRDY_FF          (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OPCR_MPP_INPUT              (0x0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OPCR_MPP_OUTPUT             (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMR_TxRDY_A                 (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMR_RxRDY_FFULL_A           (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMR_DELTA_BREAK_A           (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMR_COUNTER_READY           (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMR_TxRDY_B                 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMR_RxRDY_FFULL_B           (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMR_DELTA_BREAK_B           (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMR_INPUT_PORT_CHANGE       (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ISR_TxRDY_A                 (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ISR_RxRDY_FFULL_A           (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ISR_DELTA_BREAK_A           (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ISR_COUNTER_READY           (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ISR_TxRDY_B                 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ISR_RxRDY_FFULL_B           (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ISR_DELTA_BREAK_B           (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ISR_INPUT_PORT_CHANGE       (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ACK_INT_REQ0			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ACK_INT_REQ1			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif /* SCC2698_H_ */