^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tpci200.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * driver for the carrier TEWS TPCI-200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009-2012 CERN (www.cern.ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Nicolas Serafini, EIC2 SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _TPCI200_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _TPCI200_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/limits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/swab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ipack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TPCI200_NB_SLOT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TPCI200_NB_BAR 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TPCI200_VENDOR_ID 0x1498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TPCI200_DEVICE_ID 0x30C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TPCI200_SUBVENDOR_ID 0x1498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TPCI200_SUBDEVICE_ID 0x300A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TPCI200_CFG_MEM_BAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TPCI200_IP_INTERFACE_BAR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TPCI200_IO_ID_INT_SPACES_BAR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TPCI200_MEM16_SPACE_BAR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TPCI200_MEM8_SPACE_BAR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct tpci200_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __le16 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* writes to control should occur with the mutex held to protect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * read-modify-write operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __le16 control[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __le16 reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __le16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 reserved[242];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TPCI200_IFACE_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TPCI200_IO_SPACE_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TPCI200_IO_SPACE_INTERVAL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TPCI200_IO_SPACE_SIZE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TPCI200_ID_SPACE_OFF 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TPCI200_ID_SPACE_INTERVAL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TPCI200_ID_SPACE_SIZE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TPCI200_INT_SPACE_OFF 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TPCI200_INT_SPACE_INTERVAL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TPCI200_INT_SPACE_SIZE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TPCI200_IOIDINT_SIZE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TPCI200_MEM8_SPACE_INTERVAL 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TPCI200_MEM8_SPACE_SIZE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TPCI200_MEM16_SPACE_INTERVAL 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TPCI200_MEM16_SPACE_SIZE 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* control field in tpci200_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TPCI200_INT0_EN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TPCI200_INT1_EN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TPCI200_INT0_EDGE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TPCI200_INT1_EDGE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TPCI200_ERR_INT_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TPCI200_TIME_INT_EN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TPCI200_RECOVER_EN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TPCI200_CLK32 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* reset field in tpci200_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TPCI200_A_RESET 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TPCI200_B_RESET 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TPCI200_C_RESET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TPCI200_D_RESET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* status field in tpci200_regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TPCI200_A_TIMEOUT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TPCI200_B_TIMEOUT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TPCI200_C_TIMEOUT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TPCI200_D_TIMEOUT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TPCI200_A_ERROR 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TPCI200_B_ERROR 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TPCI200_C_ERROR 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TPCI200_D_ERROR 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TPCI200_A_INT0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TPCI200_A_INT1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TPCI200_B_INT0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TPCI200_B_INT1 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TPCI200_C_INT0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TPCI200_C_INT1 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TPCI200_D_INT0 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TPCI200_D_INT1 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TPCI200_SLOT_INT_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* PCI Configuration registers. The PCI bridge is a PLX Technology PCI9030. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LAS1_DESC 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LAS2_DESC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Bits in the LAS?_DESC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LAS_BIT_BIGENDIAN 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VME_IOID_SPACE "IOID"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VME_MEM_SPACE "MEM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * struct slot_irq - slot IRQ definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @vector Vector number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @handler Handler called when IRQ arrives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @arg Handler argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct slot_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct ipack_device *holder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) irqreturn_t (*handler)(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void *arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * struct tpci200_slot - data specific to the tpci200 slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @slot_id Slot identification gived to external interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @irq Slot IRQ infos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @io_phys IO physical base address register of the slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @id_phys ID physical base address register of the slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @int_phys INT physical base address register of the slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @mem_phys MEM physical base address register of the slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct tpci200_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct slot_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * struct tpci200_infos - informations specific of the TPCI200 tpci200.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @pci_dev PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @interface_regs Pointer to IP interface space (Bar 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @ioidint_space Pointer to IP ID, IO and INT space (Bar 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @mem8_space Pointer to MEM space (Bar 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct tpci200_infos {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct pci_device_id *id_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct tpci200_regs __iomem *interface_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void __iomem *cfg_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ipack_bus_device *ipack_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct tpci200_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spinlock_t regs_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct tpci200_slot *slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct tpci200_infos *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) phys_addr_t mod_mem[IPACK_SPACE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif /* _TPCI200_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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