Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * omap iommu: main structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008-2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef _OMAP_IOMMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define _OMAP_IOMMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define for_each_iotlb_cr(obj, n, __i, cr)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	for (__i = 0;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	     (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	     __i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct iotlb_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u32 da;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u32 pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32 pgsz, prsvd, valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u32 endian, elsz, mixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * struct omap_iommu_device - omap iommu device data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @pgtable:	page table used by an omap iommu attached to a domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * @iommu_dev:	pointer to store an omap iommu instance attached to a domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct omap_iommu_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 *pgtable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct omap_iommu *iommu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * struct omap_iommu_domain - omap iommu domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @num_iommus: number of iommus in this domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @iommus:	omap iommu device data for all iommus in this domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @dev:	Device using this domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @lock:	domain lock, should be taken when attaching/detaching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @domain:	generic domain handle used by iommu core code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct omap_iommu_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 num_iommus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct omap_iommu_device *iommus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct iommu_domain domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) struct omap_iommu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	const char	*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	void __iomem	*regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct regmap	*syscfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct device	*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct iommu_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct dentry	*debug_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	spinlock_t	iommu_lock;	/* global for this whole object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * We don't change iopgd for a situation like pgd for a task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * but share it globally for each iommu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32		*iopgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	spinlock_t	page_table_lock; /* protect iopgd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	dma_addr_t	pd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int		nr_tlb_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	void *ctx; /* iommu context: registres saved area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct cr_regs *cr_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 num_cr_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int has_bus_err_back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct iommu_device iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct iommu_group *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 pwrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * struct omap_iommu_arch_data - omap iommu private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * @iommu_dev: handle of the OMAP iommu device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * @dev: handle of the iommu device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * This is an omap iommu private data object, which binds an iommu user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * to its iommu device. This object should be placed at the iommu user's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * dev_archdata so generic IOMMU API can be used without having to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * utilize omap-specific plumbing anymore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) struct omap_iommu_arch_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct omap_iommu *iommu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct cr_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32 cam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32 ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct iotlb_lock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	short base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	short vict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * MMU Register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MMU_REVISION		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MMU_IRQSTATUS		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MMU_IRQENABLE		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MMU_WALKING_ST		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MMU_CNTL		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MMU_FAULT_AD		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MMU_TTB			0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MMU_LOCK		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MMU_LD_TLB		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MMU_CAM			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MMU_RAM			0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MMU_GFLUSH		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MMU_FLUSH_ENTRY		0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MMU_READ_CAM		0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MMU_READ_RAM		0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MMU_EMU_FAULT_AD	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MMU_GP_REG		0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MMU_REG_SIZE		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * MMU Register bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* IRQSTATUS & IRQENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MMU_IRQ_MULTIHITFAULT	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MMU_IRQ_TABLEWALKFAULT	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MMU_IRQ_EMUMISS		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MMU_IRQ_TRANSLATIONFAULT	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MMU_IRQ_TLBMISS		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define __MMU_IRQ_FAULT		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MMU_IRQ_MASK		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* MMU_CNTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MMU_CNTL_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MMU_CNTL_EML_TLB	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MMU_CNTL_TWL_EN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MMU_CNTL_MMU_EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MMU_CAM_VATAG_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MMU_CAM_VATAG_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MMU_CAM_P		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MMU_CAM_V		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MMU_CAM_PGSZ_MASK	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MMU_CAM_PGSZ_1M		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MMU_CAM_PGSZ_64K	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MMU_CAM_PGSZ_4K		(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MMU_CAM_PGSZ_16M	(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MMU_RAM_PADDR_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MMU_RAM_PADDR_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MMU_RAM_ENDIAN_SHIFT	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MMU_RAM_ENDIAN_MASK	BIT(MMU_RAM_ENDIAN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MMU_RAM_ENDIAN_LITTLE	(0 << MMU_RAM_ENDIAN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MMU_RAM_ENDIAN_BIG	BIT(MMU_RAM_ENDIAN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MMU_RAM_ELSZ_SHIFT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MMU_RAM_ELSZ_MASK	(3 << MMU_RAM_ELSZ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MMU_RAM_ELSZ_8		(0 << MMU_RAM_ELSZ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MMU_RAM_ELSZ_16		(1 << MMU_RAM_ELSZ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MMU_RAM_ELSZ_32		(2 << MMU_RAM_ELSZ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MMU_RAM_ELSZ_NONE	(3 << MMU_RAM_ELSZ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MMU_RAM_MIXED_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MMU_RAM_MIXED_MASK	BIT(MMU_RAM_MIXED_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MMU_RAM_MIXED		MMU_RAM_MIXED_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MMU_GP_REG_BUS_ERR_BACK_EN	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define get_cam_va_mask(pgsz)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DSP_SYS_REVISION		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DSP_SYS_MMU_CONFIG		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DSP_SYS_MMU_CONFIG_EN_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * utilities for super page(16MB, 1MB, 64KB and 4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define iopgsz_max(bytes)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	(((bytes) >= SZ_16M) ? SZ_16M :		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 ((bytes) >= SZ_1M)  ? SZ_1M  :		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 ((bytes) >= SZ_64K) ? SZ_64K :		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 ((bytes) >= SZ_4K)  ? SZ_4K  :	0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define bytes_to_iopgsz(bytes)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define iopgsz_to_bytes(iopgsz)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	(((iopgsz) == MMU_CAM_PGSZ_16M)	? SZ_16M :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 ((iopgsz) == MMU_CAM_PGSZ_1M)	? SZ_1M  :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 ((iopgsz) == MMU_CAM_PGSZ_64K)	? SZ_64K :	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 ((iopgsz) == MMU_CAM_PGSZ_4K)	? SZ_4K  : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * global functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #ifdef CONFIG_OMAP_IOMMU_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void omap_iommu_debugfs_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void omap_iommu_debugfs_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) void omap_iommu_debugfs_add(struct omap_iommu *obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void omap_iommu_debugfs_remove(struct omap_iommu *obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static inline void omap_iommu_debugfs_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline void omap_iommu_debugfs_exit(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * register accessors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return __raw_readl(obj->regbase + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	__raw_writel(val, obj->regbase + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static inline int iotlb_cr_valid(struct cr_regs *cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (!cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return cr->cam & MMU_CAM_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif /* _OMAP_IOMMU_H */