^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IOMMU API for MTK architected m4u v1 implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015-2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Honghui Zhang <honghui.zhang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on driver/iommu/mtk_iommu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/barrier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/dma-iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <dt-bindings/memory/mt2701-larb-port.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <soc/mediatek/smi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "mtk_iommu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_MMU_PT_BASE_ADDR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define F_ALL_INVLD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define F_MMU_INV_RANGE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define F_INVLD_EN0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define F_INVLD_EN1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define F_MMU_FAULT_VA_MSK 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MTK_PROTECT_PA_ALIGN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_MMU_CTRL_REG 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define F_MMU_CTRL_COHERENT_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_MMU_IVRP_PADDR 0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_MMU_INT_CONTROL 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define F_INT_TRANSLATION_FAULT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define F_INT_INVALID_PA_FAULT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define F_INT_TABLE_WALK_FAULT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define F_INT_TLB_MISS_FAULT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define F_INT_CLR_BIT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_MMU_FAULT_ST 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_MMU_FAULT_VA 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_MMU_INVLD_PA 0x22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_MMU_INT_ID 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_MMU_INVALIDATE 0x5c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_MMU_INVLD_START_A 0x5c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_MMU_INVLD_END_A 0x5c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_MMU_INV_SEL 0x5d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_MMU_STANDARD_AXI_MODE 0x5e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_MMU_DCM 0x5f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define F_MMU_DCM_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_MMU_CPE_DONE 0x60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define F_DESC_VALID 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define F_DESC_NONSEC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* MTK generation one iommu HW only support 4K size mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MT2701_IOMMU_PAGE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * MTK m4u support 4GB iova address space, and only support 4K page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * mapping. So the pagetable size should be exactly as 4M.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define M2701_IOMMU_PGT_SIZE SZ_4M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct mtk_iommu_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spinlock_t pgtlock; /* lock for page table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct iommu_domain domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 *pgt_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dma_addr_t pgt_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mtk_iommu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return container_of(dom, struct mtk_iommu_domain, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const int mt2701_m4u_in_larb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline int mt2701_m4u_to_larb(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if ((id) >= mt2701_m4u_in_larb[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline int mt2701_m4u_to_port(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int larb = mt2701_m4u_to_larb(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return id - mt2701_m4u_in_larb[larb];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) data->base + REG_MMU_INV_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) wmb(); /* Make sure the tlb flush all done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long iova, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) data->base + REG_MMU_INV_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) data->base + REG_MMU_INVLD_START_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) data->base + REG_MMU_INVLD_END_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tmp, tmp != 0, 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_warn(data->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "Partial TLB flush timed out, falling back to full flush\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mtk_iommu_tlb_flush_all(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Clear the CPE status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mtk_iommu_data *data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct mtk_iommu_domain *dom = data->m4u_dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 int_state, regval, fault_iova, fault_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int fault_larb, fault_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Read error information from registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) fault_iova &= F_MMU_FAULT_VA_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) regval = readl_relaxed(data->base + REG_MMU_INT_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) fault_larb = MT2701_M4U_TF_LARB(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) fault_port = MT2701_M4U_TF_PORT(regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * MTK v1 iommu HW could not determine whether the fault is read or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * write fault, report as read fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IOMMU_FAULT_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err_ratelimited(data->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int_state, fault_iova, fault_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) fault_larb, fault_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Interrupt clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) regval |= F_INT_CLR_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mtk_iommu_tlb_flush_all(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void mtk_iommu_config(struct mtk_iommu_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct device *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct mtk_smi_larb_iommu *larb_mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int larbid, portid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < fwspec->num_ids; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) portid = mt2701_m4u_to_port(fwspec->ids[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) larb_mmu = &data->larb_imu[larbid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_dbg(dev, "%s iommu port: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) enable ? "enable" : "disable", portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct mtk_iommu_domain *dom = data->m4u_dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) spin_lock_init(&dom->pgtlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) &dom->pgt_pa, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!dom->pgt_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dom->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct mtk_iommu_domain *dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (type != IOMMU_DOMAIN_UNMANAGED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dom = kzalloc(sizeof(*dom), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!dom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return &dom->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void mtk_iommu_domain_free(struct iommu_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct mtk_iommu_domain *dom = to_mtk_domain(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct mtk_iommu_data *data = dom->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dom->pgt_va, dom->pgt_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) kfree(to_mtk_domain(domain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int mtk_iommu_attach_device(struct iommu_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct mtk_iommu_domain *dom = to_mtk_domain(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct dma_iommu_mapping *mtk_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Only allow the domain created internally. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mtk_mapping = data->mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (mtk_mapping->domain != domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!data->m4u_dom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) data->m4u_dom = dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = mtk_iommu_domain_finalise(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) data->m4u_dom = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mtk_iommu_config(data, dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void mtk_iommu_detach_device(struct iommu_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) mtk_iommu_config(data, dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct mtk_iommu_domain *dom = to_mtk_domain(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 pabase = (u32)paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int map_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock_irqsave(&dom->pgtlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) for (i = 0; i < page_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (pgt_base_iova[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) memset(pgt_base_iova, 0, i * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pabase += MT2701_IOMMU_PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) map_size += MT2701_IOMMU_PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) spin_unlock_irqrestore(&dom->pgtlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mtk_iommu_tlb_flush_range(dom->data, iova, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return map_size == size ? 0 : -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static size_t mtk_iommu_unmap(struct iommu_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned long iova, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct iommu_iotlb_gather *gather)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct mtk_iommu_domain *dom = to_mtk_domain(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) spin_lock_irqsave(&dom->pgtlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) memset(pgt_base_iova, 0, page_num * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_unlock_irqrestore(&dom->pgtlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mtk_iommu_tlb_flush_range(dom->data, iova, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dma_addr_t iova)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct mtk_iommu_domain *dom = to_mtk_domain(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) phys_addr_t pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spin_lock_irqsave(&dom->pgtlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) spin_unlock_irqrestore(&dom->pgtlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct iommu_ops mtk_iommu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * MTK generation one iommu HW only support one iommu domain, and all the client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * sharing the same iova address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int mtk_iommu_create_mapping(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct mtk_iommu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct platform_device *m4updev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct dma_iommu_mapping *mtk_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (args->args_count != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) args->args_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!fwspec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) fwspec = dev_iommu_fwspec_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!dev_iommu_priv_get(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Get the m4u device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) m4updev = of_find_device_by_node(args->np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (WARN_ON(!m4updev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = iommu_fwspec_add_ids(dev, args->args, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) data = dev_iommu_priv_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mtk_mapping = data->mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!mtk_mapping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* MTK iommu support 4GB iova address space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0, 1ULL << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (IS_ERR(mtk_mapping))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return PTR_ERR(mtk_mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) data->mapping = mtk_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int mtk_iommu_def_domain_type(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return IOMMU_DOMAIN_UNMANAGED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct of_phandle_args iommu_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct of_phandle_iterator it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct mtk_iommu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) of_for_each_phandle(&it, err, dev->of_node, "iommus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "#iommu-cells", -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int count = of_phandle_iterator_args(&it, iommu_spec.args,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MAX_PHANDLE_ARGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) iommu_spec.np = of_node_get(it.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) iommu_spec.args_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mtk_iommu_create_mapping(dev, &iommu_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* dev->iommu_fwspec might have changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) fwspec = dev_iommu_fwspec_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) of_node_put(iommu_spec.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!fwspec || fwspec->ops != &mtk_iommu_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ERR_PTR(-ENODEV); /* Not a iommu client device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) data = dev_iommu_priv_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return &data->iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void mtk_iommu_probe_finalize(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct dma_iommu_mapping *mtk_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct mtk_iommu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) data = dev_iommu_priv_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mtk_mapping = data->mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err = arm_iommu_attach_device(dev, mtk_mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void mtk_iommu_release_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!fwspec || fwspec->ops != &mtk_iommu_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) iommu_fwspec_free(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = clk_prepare_enable(data->bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) regval = F_INT_TRANSLATION_FAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) F_INT_MAIN_MULTI_HIT_FAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) F_INT_INVALID_PA_FAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) F_INT_ENTRY_REPLACEMENT_FAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) F_INT_TABLE_WALK_FAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) F_INT_TLB_MISS_FAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) F_INT_PFH_DMA_FIFO_OVERFLOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) F_INT_MISS_DMA_FIFO_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* protect memory,hw will write here while translation fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) writel_relaxed(data->protect_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) data->base + REG_MMU_IVRP_PADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_name(data->dev), (void *)data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) clk_disable_unprepare(data->bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct iommu_ops mtk_iommu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .domain_alloc = mtk_iommu_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .domain_free = mtk_iommu_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .attach_dev = mtk_iommu_attach_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .detach_dev = mtk_iommu_detach_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .map = mtk_iommu_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .unmap = mtk_iommu_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .iova_to_phys = mtk_iommu_iova_to_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .probe_device = mtk_iommu_probe_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .probe_finalize = mtk_iommu_probe_finalize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .release_device = mtk_iommu_release_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .def_domain_type = mtk_iommu_def_domain_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .device_group = generic_device_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct of_device_id mtk_iommu_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { .compatible = "mediatek,mt2701-m4u", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct component_master_ops mtk_iommu_com_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .bind = mtk_iommu_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .unbind = mtk_iommu_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int mtk_iommu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct mtk_iommu_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct component_match *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct of_phandle_args larb_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct of_phandle_iterator it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) void *protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int larb_nr, ret, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) data->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Protect memory. HW will access here while translation fault.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!protect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) data->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (IS_ERR(data->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return PTR_ERR(data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) data->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (data->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) data->bclk = devm_clk_get(dev, "bclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (IS_ERR(data->bclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return PTR_ERR(data->bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) larb_nr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) of_for_each_phandle(&it, err, dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "mediatek,larbs", NULL, 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct platform_device *plarbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int count = of_phandle_iterator_args(&it, larb_spec.args,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MAX_PHANDLE_ARGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) larb_spec.np = of_node_get(it.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!of_device_is_available(larb_spec.np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) plarbdev = of_find_device_by_node(larb_spec.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!plarbdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) plarbdev = of_platform_device_create(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) larb_spec.np, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) platform_bus_type.dev_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!plarbdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) of_node_put(larb_spec.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) data->larb_imu[larb_nr].dev = &plarbdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) component_match_add_release(dev, &match, release_of,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) compare_of, larb_spec.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) larb_nr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = mtk_iommu_hw_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_name(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) iommu_device_set_ops(&data->iommu, &mtk_iommu_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = iommu_device_register(&data->iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!iommu_present(&platform_bus_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int mtk_iommu_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct mtk_iommu_data *data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) iommu_device_sysfs_remove(&data->iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) iommu_device_unregister(&data->iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (iommu_present(&platform_bus_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) bus_set_iommu(&platform_bus_type, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) clk_disable_unprepare(data->bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) devm_free_irq(&pdev->dev, data->irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) component_master_del(&pdev->dev, &mtk_iommu_com_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int __maybe_unused mtk_iommu_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct mtk_iommu_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct mtk_iommu_suspend_reg *reg = &data->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) reg->standard_axi_mode = readl_relaxed(base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) REG_MMU_STANDARD_AXI_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int __maybe_unused mtk_iommu_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct mtk_iommu_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct mtk_iommu_suspend_reg *reg = &data->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) void __iomem *base = data->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) writel_relaxed(reg->standard_axi_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) base + REG_MMU_STANDARD_AXI_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const struct dev_pm_ops mtk_iommu_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static struct platform_driver mtk_iommu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .probe = mtk_iommu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .remove = mtk_iommu_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = "mtk-iommu-v1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .of_match_table = mtk_iommu_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .pm = &mtk_iommu_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int __init m4u_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return platform_driver_register(&mtk_iommu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) subsys_initcall(m4u_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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