^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015-2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Honghui Zhang <honghui.zhang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _MTK_IOMMU_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _MTK_IOMMU_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io-pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <soc/mediatek/smi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/memory/mtk-memory-port.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MTK_LARB_COM_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MTK_LARB_SUBCOM_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MTK_IOMMU_GROUP_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mtk_iommu_suspend_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 standard_axi_mode;/* v1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 misc_ctrl;/* v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 dcm_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 int_control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 int_main_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 ivrp_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 vld_pa_rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 wr_len_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum mtk_iommu_plat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) M4U_MT2701,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) M4U_MT2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) M4U_MT6779,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) M4U_MT8167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) M4U_MT8173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) M4U_MT8183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) M4U_MT8192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mtk_iommu_iova_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct mtk_iommu_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum mtk_iommu_plat m4u_plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 inv_sel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int iova_region_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const struct mtk_iommu_iova_region *iova_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mtk_iommu_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct mtk_iommu_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk *bclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) phys_addr_t protect_base; /* protect memory base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mtk_iommu_suspend_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct mtk_iommu_domain *m4u_dom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bool enable_4GB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) spinlock_t tlb_lock; /* lock for tlb range flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct iommu_device iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct mtk_iommu_plat_data *plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct device *smicomm_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline int compare_of(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return dev->of_node == data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline void release_of(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) of_node_put(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline int mtk_iommu_bind(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct mtk_iommu_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return component_bind_all(dev, &data->larb_imu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void mtk_iommu_unbind(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct mtk_iommu_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) component_unbind_all(dev, &data->larb_imu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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