^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef MSM_IOMMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define MSM_IOMMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Sharability attributes of MSM IOMMU mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MSM_IOMMU_ATTR_NON_SH 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MSM_IOMMU_ATTR_SH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Cacheability attributes of MSM IOMMU mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MSM_IOMMU_ATTR_NONCACHED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MSM_IOMMU_ATTR_CACHED_WT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Mask for the cache policy attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MSM_IOMMU_CP_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Maximum number of Machine IDs that we are allowing to be mapped to the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * context bank. The number of MIDs mapped to the same CB does not affect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * performance, but there is a practical limit on how many distinct MIDs may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * be present. These mappings are typically determined at design time and are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * not expected to change at run time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAX_NUM_MIDS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Maximum number of context banks that can be present in IOMMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IOMMU_MAX_CBS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * struct msm_iommu_dev - a single IOMMU hardware instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * ncb Number of context banks present on this IOMMU HW instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * dev: IOMMU device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * irq: Interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * clk: The bus clock for this IOMMU hardware instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * pclk: The clock for the IOMMU bus interconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * dev_node: list head in qcom_iommu_device_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * dom_node: list head for domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * ctx_list: list of 'struct msm_iommu_ctx_dev'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * context_map: Bitmap to track allocated context banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct msm_iommu_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int ncb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct list_head dev_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct list_head dom_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct list_head ctx_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct iommu_device iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * struct msm_iommu_ctx_dev - an IOMMU context bank instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * of_node node ptr of client device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * num Index of this context bank within the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * mids List of Machine IDs that are to be mapped into this context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * bank, terminated by -1. The MID is a set of signals on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * AXI bus that identifies the function associated with a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * memory request. (See ARM spec).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * num_mids Total number of mids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * node list head in ctx_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct msm_iommu_ctx_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int mids[MAX_NUM_MIDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int num_mids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Interrupt handler for the IOMMU context fault interrupt. Hooking the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * interrupt is not supported in the API yet, but this will print an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * message and dump useful IOMMU registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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