^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright © 2018 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Gayatri Kammela <gayatri.kammela@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Sohil Mehta <sohil.mehta@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jacob Pan <jacob.jun.pan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Lu Baolu <baolu.lu@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmar.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/intel-iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/irq_remapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pasid.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct tbl_walk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u16 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u16 devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 pasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct root_entry *rt_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct context_entry *ctx_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct pasid_entry *pasid_tbl_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct iommu_regset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const char *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IOMMU_REGSET_ENTRY(_reg_) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { DMAR_##_reg_##_REG, __stringify(_reg_) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct iommu_regset iommu_regs_32[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) IOMMU_REGSET_ENTRY(VER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) IOMMU_REGSET_ENTRY(GCMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) IOMMU_REGSET_ENTRY(GSTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) IOMMU_REGSET_ENTRY(FSTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) IOMMU_REGSET_ENTRY(FECTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) IOMMU_REGSET_ENTRY(FEDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) IOMMU_REGSET_ENTRY(FEADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) IOMMU_REGSET_ENTRY(FEUADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IOMMU_REGSET_ENTRY(PMEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) IOMMU_REGSET_ENTRY(PLMBASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) IOMMU_REGSET_ENTRY(PLMLIMIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) IOMMU_REGSET_ENTRY(ICS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) IOMMU_REGSET_ENTRY(PRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) IOMMU_REGSET_ENTRY(PECTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) IOMMU_REGSET_ENTRY(PEDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) IOMMU_REGSET_ENTRY(PEADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) IOMMU_REGSET_ENTRY(PEUADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct iommu_regset iommu_regs_64[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) IOMMU_REGSET_ENTRY(CAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IOMMU_REGSET_ENTRY(ECAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IOMMU_REGSET_ENTRY(RTADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) IOMMU_REGSET_ENTRY(CCMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) IOMMU_REGSET_ENTRY(AFLOG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) IOMMU_REGSET_ENTRY(PHMBASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) IOMMU_REGSET_ENTRY(PHMLIMIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) IOMMU_REGSET_ENTRY(IQH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) IOMMU_REGSET_ENTRY(IQT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) IOMMU_REGSET_ENTRY(IQA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) IOMMU_REGSET_ENTRY(IRTA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) IOMMU_REGSET_ENTRY(PQH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) IOMMU_REGSET_ENTRY(PQT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) IOMMU_REGSET_ENTRY(PQA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) IOMMU_REGSET_ENTRY(MTRRCAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) IOMMU_REGSET_ENTRY(MTRRDEF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) IOMMU_REGSET_ENTRY(VCCAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) IOMMU_REGSET_ENTRY(VCMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) IOMMU_REGSET_ENTRY(VCRSP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int iommu_regset_show(struct seq_file *m, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct dmar_drhd_unit *drhd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct intel_iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) for_each_active_iommu(iommu, drhd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!drhd->reg_base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) seq_puts(m, "IOMMU: Invalid base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) iommu->name, drhd->reg_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) seq_puts(m, "Name\t\t\tOffset\t\tContents\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Publish the contents of the 64-bit hardware registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * by adding the offset to the pointer (virtual address).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) raw_spin_lock_irqsave(&iommu->register_lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) iommu_regs_32[i].regs, iommu_regs_32[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) iommu_regs_64[i].regs, iommu_regs_64[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEFINE_SHOW_ATTRIBUTE(iommu_regset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline void print_tbl_walk(struct seq_file *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct tbl_walk *tbl_wlk = m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tbl_wlk->ctx_entry->lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * A legacy mode DMAR doesn't support PASID, hence default it to -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * indicating that it's invalid. Also, default all PASID related fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!tbl_wlk->pasid_tbl_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (u64)0, (u64)0, (u64)0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tbl_wlk->pasid_tbl_entry->val[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tbl_wlk->pasid_tbl_entry->val[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u16 dir_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct tbl_walk *tbl_wlk = m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 tbl_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (tbl_idx = 0; tbl_idx < PASID_TBL_ENTRIES; tbl_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (pasid_pte_is_present(tbl_entry)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tbl_wlk->pasid_tbl_entry = tbl_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) print_tbl_walk(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tbl_entry++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u16 pasid_dir_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct pasid_dir_entry *dir_entry = phys_to_virt(pasid_dir_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct pasid_entry *pasid_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u16 dir_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) for (dir_idx = 0; dir_idx < pasid_dir_size; dir_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pasid_tbl = get_pasid_table_from_pde(dir_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (pasid_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pasid_tbl_walk(m, pasid_tbl, dir_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dir_entry++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct context_entry *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 devfn, pasid_dir_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u64 pasid_dir_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (devfn = 0; devfn < 256; devfn++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct tbl_walk tbl_wlk = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Scalable mode root entry points to upper scalable mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * context table and lower scalable mode context table. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * scalable mode context table has 128 context entries where as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * legacy mode context table has 256 context entries. So in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * scalable mode, the context entries for former 128 devices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * in the lower scalable mode context table, while the latter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 128 devices are in the upper scalable mode context table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * In scalable mode, when devfn > 127, iommu_context_addr()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * automatically refers to upper scalable mode context table and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * hence the caller doesn't have to worry about differences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * between scalable mode and non scalable mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) context = iommu_context_addr(iommu, bus, devfn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!context_present(context))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tbl_wlk.bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tbl_wlk.devfn = devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tbl_wlk.rt_entry = &iommu->root_entry[bus];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tbl_wlk.ctx_entry = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) m->private = &tbl_wlk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pasid_dir_size = get_pasid_dir_size(context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) print_tbl_walk(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u16 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_lock_irqsave(&iommu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (u64)virt_to_phys(iommu->root_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * No need to check if the root entry is present or not because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * iommu_context_addr() performs the same check before returning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * context entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) for (bus = 0; bus < 256; bus++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ctx_tbl_walk(m, iommu, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) spin_unlock_irqrestore(&iommu->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int dmar_translation_struct_show(struct seq_file *m, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct dmar_drhd_unit *drhd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct intel_iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) for_each_active_iommu(iommu, drhd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!(sts & DMA_GSTS_TES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) seq_printf(m, "DMA Remapping is not enabled on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) iommu->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) root_tbl_walk(m, iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static inline unsigned long level_to_directory_size(int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dump_page_info(struct seq_file *m, unsigned long iova, u64 *path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) iova >> VTD_PAGE_SHIFT, path[5], path[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) path[3], path[2], path[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int level, unsigned long start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u64 *path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (level > 5 || level < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (i = 0; i < BIT_ULL(VTD_STRIDE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) i++, pde++, start += level_to_directory_size(level)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!dma_pte_present(pde))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) path[level] = pde->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (dma_pte_superpage(pde) || level == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dump_page_info(m, start, path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) level - 1, start, path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) path[level] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int show_device_domain_translation(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct dmar_domain *domain = find_domain(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct seq_file *m = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u64 path[6] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) seq_printf(m, "Device %s with pasid %d @0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_name(dev), domain->default_pasid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (u64)virt_to_phys(domain->pgd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) seq_puts(m, "IOVA_PFN\t\tPML5E\t\t\tPML4E\t\t\tPDPE\t\t\tPDE\t\t\tPTE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int domain_translation_struct_show(struct seq_file *m, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) spin_lock_irqsave(&device_domain_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = bus_for_each_dev(&pci_bus_type, NULL, m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) show_device_domain_translation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) spin_unlock_irqrestore(&device_domain_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DEFINE_SHOW_ATTRIBUTE(domain_translation_struct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void invalidation_queue_entry_show(struct seq_file *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct intel_iommu *iommu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int index, shift = qi_shift(iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct qi_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ecap_smts(iommu->ecap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tqw2\t\t\tqw3\t\t\tstatus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tstatus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (index = 0; index < QI_LENGTH; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) offset = index << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) desc = iommu->qi->desc + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ecap_smts(iommu->ecap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) seq_printf(m, "%5d\t%016llx\t%016llx\t%016llx\t%016llx\t%016x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) index, desc->qw0, desc->qw1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) desc->qw2, desc->qw3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) iommu->qi->desc_status[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) seq_printf(m, "%5d\t%016llx\t%016llx\t%016x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) index, desc->qw0, desc->qw1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) iommu->qi->desc_status[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int invalidation_queue_show(struct seq_file *m, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct dmar_drhd_unit *drhd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct intel_iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct q_inval *qi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) for_each_active_iommu(iommu, drhd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) qi = iommu->qi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) shift = qi_shift(iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!qi || !ecap_qis(iommu->ecap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) raw_spin_lock_irqsave(&qi->q_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) (u64)virt_to_phys(qi->desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) invalidation_queue_entry_show(m, iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) raw_spin_unlock_irqrestore(&qi->q_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DEFINE_SHOW_ATTRIBUTE(invalidation_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #ifdef CONFIG_IRQ_REMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void ir_tbl_remap_entry_show(struct seq_file *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct intel_iommu *iommu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct irte *ri_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) seq_puts(m, " Entry SrcID DstID Vct IRTE_high\t\tIRTE_low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ri_entry = &iommu->ir_table->base[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!ri_entry->present || ri_entry->p_pst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x %016llx\t%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) idx, PCI_BUS_NUM(ri_entry->sid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ri_entry->dest_id, ri_entry->vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ri_entry->high, ri_entry->low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static void ir_tbl_posted_entry_show(struct seq_file *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct intel_iommu *iommu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct irte *pi_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) seq_puts(m, " Entry SrcID PDA_high PDA_low Vct IRTE_high\t\tIRTE_low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pi_entry = &iommu->ir_table->base[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!pi_entry->present || !pi_entry->p_pst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x %016llx\t%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) idx, PCI_BUS_NUM(pi_entry->sid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pi_entry->pda_h, pi_entry->pda_l << 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pi_entry->vector, pi_entry->high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pi_entry->low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * For active IOMMUs go through the Interrupt remapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * table and print valid entries in a table format for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Remapped and Posted Interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int ir_translation_struct_show(struct seq_file *m, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct dmar_drhd_unit *drhd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct intel_iommu *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u64 irta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rcu_read_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) for_each_active_iommu(iommu, drhd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!ecap_ir_support(iommu->ecap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) iommu->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) irta = virt_to_phys(iommu->ir_table->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) seq_printf(m, " IR table address:%llx\n", irta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ir_tbl_remap_entry_show(m, iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) seq_puts(m, "Interrupt Remapping is not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) seq_puts(m, "****\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) for_each_active_iommu(iommu, drhd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!cap_pi_support(iommu->cap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) iommu->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (iommu->ir_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) irta = virt_to_phys(iommu->ir_table->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) seq_printf(m, " IR table address:%llx\n", irta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ir_tbl_posted_entry_show(m, iommu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) seq_puts(m, "Interrupt Remapping is not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) rcu_read_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) DEFINE_SHOW_ATTRIBUTE(ir_translation_struct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) void __init intel_iommu_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct dentry *intel_iommu_debug = debugfs_create_dir("intel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) iommu_debugfs_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &iommu_regset_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) debugfs_create_file("dmar_translation_struct", 0444, intel_iommu_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) NULL, &dmar_translation_struct_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) debugfs_create_file("domain_translation_struct", 0444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) intel_iommu_debug, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &domain_translation_struct_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) debugfs_create_file("invalidation_queue", 0444, intel_iommu_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) NULL, &invalidation_queue_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #ifdef CONFIG_IRQ_REMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) NULL, &ir_translation_struct_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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