Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __FSL_PAMU_DOMAIN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __FSL_PAMU_DOMAIN_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "fsl_pamu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct dma_window {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	phys_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	int valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	int prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct fsl_dma_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	 * Indicates the geometry size for the domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	 * This would be set when the geometry is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	 * configured for the domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	dma_addr_t			geom_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	 * Number of windows assocaited with this domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	 * During domain initialization, it is set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	 * the maximum number of subwindows allowed for a LIODN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	 * Minimum value for this is 1 indicating a single PAMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	 * window, without any sub windows. Value can be set/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	 * queried by set_attr/get_attr API for DOMAIN_ATTR_WINDOWS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	 * Value can only be set once the geometry has been configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u32				win_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	 * win_arr contains information of the configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	 * windows for a domain. This is allocated only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	 * when the number of windows for the domain are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	 * set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	struct dma_window		*win_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	/* list of devices associated with the domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct list_head		devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	/* dma_domain states:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	 * mapped - A particular mapping has been created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	 * within the configured geometry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	 * enabled - DMA has been enabled for the given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	 * domain. This translates to setting of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	 * valid bit for the primary PAACE in the PAMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	 * PAACT table. Domain geometry should be set and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	 * it must have a valid mapping before DMA can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	 * enabled for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	int				mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	int				enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	/* stash_id obtained from the stash attribute details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	u32				stash_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	struct pamu_stash_attribute	dma_stash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	u32				snoop_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	struct iommu_domain		iommu_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	spinlock_t			domain_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* domain-device relationship */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device_domain_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	struct list_head link;	/* link to domain siblings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	u32 liodn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	struct fsl_dma_domain *domain; /* pointer to domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif  /* __FSL_PAMU_DOMAIN_H */