^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __FSL_PAMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __FSL_PAMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/fsl_pamu_stash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Bit Field macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * v = bit field variable; m = mask, m##_SHIFT = shift, x = value to load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << m##_SHIFT) & (m)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define get_bf(v, m) (((v) & (m)) >> m##_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* PAMU CCSR space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PAMU_PE 0x40000000 /* enable PAMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* PAMU_OFFSET to the next pamu space in ccsr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PAMU_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PAMU_MMAP_REGS_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct pamu_mmap_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 ppbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 ppbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 pplah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 pplal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 spbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 spbal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 splah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 splal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 obah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 obal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 olah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 olal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* PAMU Error Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PAMU_POES1 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PAMU_POES2 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PAMU_POEAH 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PAMU_POEAL 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PAMU_AVS1 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PAMU_AVS1_AV 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PAMU_AVS1_OTV 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PAMU_AVS1_APV 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PAMU_AVS1_WAV 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PAMU_AVS1_LAV 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PAMU_AVS1_GCV 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PAMU_AVS1_PDV 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PAMU_AV_MASK (PAMU_AVS1_AV | PAMU_AVS1_OTV | PAMU_AVS1_APV | PAMU_AVS1_WAV \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) | PAMU_AVS1_LAV | PAMU_AVS1_GCV | PAMU_AVS1_PDV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PAMU_AVS1_LIODN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PAMU_AVS2 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PAMU_AVAH 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PAMU_AVAL 0x005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PAMU_EECTL 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PAMU_EEDIS 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PAMU_EEINTEN 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PAMU_EEDET 0x006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PAMU_EEATTR 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PAMU_EEAHI 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PAMU_EEALO 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PAMU_EEDHI 0X007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PAMU_EEDLO 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PAMU_EECC 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PAMU_UDAD 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* PAMU Revision Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PAMU_PR1 0x0BF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PAMU_PR2 0x0BFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* PAMU version mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PAMU_PR1_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* PAMU Capabilities Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PAMU_PC1 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PAMU_PC2 0x0C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PAMU_PC3 0x0C08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PAMU_PC4 0x0C0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* PAMU Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PAMU_PC 0x0C10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* PAMU control defs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PAMU_CONTROL 0x0C10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PAMU_PC_PGC 0x80000000 /* PAMU gate closed bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PAMU_PC_PE 0x40000000 /* PAMU enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PAMU_PC_OCE 0x00001000 /* OMT cache enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PAMU_PFA1 0x0C14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PAMU_PFA2 0x0C18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PAMU_PC2_MLIODN(X) ((X) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* PAMU Interrupt control and Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PAMU_PICS 0x0C1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PAMU_ACCESS_VIOLATION_STAT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PAMU_ACCESS_VIOLATION_ENABLE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* PAMU Debug Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PAMU_PD1 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PAMU_PD2 0x0F04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PAMU_PD3 0x0F08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PAMU_PD4 0x0F0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PAACE_AP_PERMS_DENIED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PAACE_AP_PERMS_QUERY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PAACE_AP_PERMS_UPDATE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PAACE_AP_PERMS_ALL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PAACE_DD_TO_HOST 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PAACE_DD_TO_IO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PAACE_PT_PRIMARY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PAACE_PT_SECONDARY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PAACE_V_INVALID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PAACE_V_VALID 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PAACE_MW_SUBWINDOWS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PAACE_WSE_4K 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PAACE_WSE_8K 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PAACE_WSE_16K 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PAACE_WSE_32K 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PAACE_WSE_64K 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PAACE_WSE_128K 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PAACE_WSE_256K 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PAACE_WSE_512K 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PAACE_WSE_1M 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PAACE_WSE_2M 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PAACE_WSE_4M 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PAACE_WSE_8M 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PAACE_WSE_16M 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PAACE_WSE_32M 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PAACE_WSE_64M 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PAACE_WSE_128M 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PAACE_WSE_256M 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PAACE_WSE_512M 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PAACE_WSE_1G 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PAACE_WSE_2G 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PAACE_WSE_4G 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PAACE_DID_PCI_EXPRESS_1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PAACE_DID_PCI_EXPRESS_2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PAACE_DID_PCI_EXPRESS_3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PAACE_DID_PCI_EXPRESS_4 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PAACE_DID_LOCAL_BUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PAACE_DID_SRIO 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PAACE_DID_MEM_1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PAACE_DID_MEM_2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PAACE_DID_MEM_3 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PAACE_DID_MEM_4 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PAACE_DID_MEM_1_2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PAACE_DID_MEM_3_4 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PAACE_DID_MEM_1_4 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PAACE_DID_BM_SW_PORTAL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PAACE_DID_PAMU 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PAACE_DID_CAAM 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PAACE_DID_QM_SW_PORTAL 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PAACE_DID_CORE0_INST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PAACE_DID_CORE0_DATA 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PAACE_DID_CORE1_INST 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PAACE_DID_CORE1_DATA 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PAACE_DID_CORE2_INST 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PAACE_DID_CORE2_DATA 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PAACE_DID_CORE3_INST 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PAACE_DID_CORE3_DATA 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PAACE_DID_CORE4_INST 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PAACE_DID_CORE4_DATA 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PAACE_DID_CORE5_INST 0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PAACE_DID_CORE5_DATA 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PAACE_DID_CORE6_INST 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PAACE_DID_CORE6_DATA 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PAACE_DID_CORE7_INST 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PAACE_DID_CORE7_DATA 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PAACE_DID_BROADCAST 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PAACE_ATM_NO_XLATE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PAACE_ATM_WINDOW_XLATE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PAACE_ATM_PAGE_XLATE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PAACE_ATM_WIN_PG_XLATE (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PAACE_OTM_NO_XLATE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PAACE_OTM_IMMEDIATE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PAACE_OTM_INDEXED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PAACE_OTM_RESERVED 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PAACE_M_COHERENCE_REQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PAACE_PID_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PAACE_PID_1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PAACE_PID_2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PAACE_PID_3 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PAACE_PID_4 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PAACE_PID_5 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PAACE_PID_6 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PAACE_PID_7 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PAACE_TCEF_FORMAT0_8B 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PAACE_TCEF_FORMAT1_RSVD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Hard coded value for the PAACT size to accommodate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * maximum LIODN value generated by u-boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PAACE_NUMBER_ENTRIES 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Hard coded value for the SPAACT size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SPAACE_NUMBER_ENTRIES 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OME_NUMBER_ENTRIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* PAACE Bit Field Defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PPAACE_AF_WBAL 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PPAACE_AF_WBAL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PPAACE_AF_WSE 0x00000fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PPAACE_AF_WSE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PPAACE_AF_MW 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PPAACE_AF_MW_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SPAACE_AF_LIODN 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SPAACE_AF_LIODN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PAACE_AF_AP 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PAACE_AF_AP_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PAACE_AF_DD 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PAACE_AF_DD_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PAACE_AF_PT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PAACE_AF_PT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PAACE_AF_V 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PAACE_AF_V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PAACE_DA_HOST_CR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PAACE_DA_HOST_CR_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PAACE_IA_CID 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PAACE_IA_CID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PAACE_IA_WCE 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PAACE_IA_WCE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PAACE_IA_ATM 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PAACE_IA_ATM_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PAACE_IA_OTM 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PAACE_IA_OTM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PAACE_WIN_TWBAL 0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PAACE_WIN_TWBAL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PAACE_WIN_SWSE 0x00000fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PAACE_WIN_SWSE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* PAMU Data Structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* primary / secondary paact structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct paace {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* PAACE Offset 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 wbah; /* only valid for Primary PAACE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 addr_bitfields; /* See P/S PAACE_AF_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* PAACE Offset 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Interpretation of first 32 bits dependent on DD above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Destination ID, see PAACE_DID_* defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 did;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Partition ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Snoop ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 snpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* coherency_required : 1 reserved : 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 coherency_required; /* See PAACE_DA_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } to_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Destination ID, see PAACE_DID_* defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 did;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } to_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } domain_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Implementation attributes + window count + address & operation translation modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 impl_attr; /* See PAACE_IA_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PAACE Offset 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Translated window base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 twbah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 win_bitfields; /* See PAACE_WIN_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* PAACE Offset 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* first secondary paace entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 fspi; /* only valid for Primary PAACE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 ioea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 moea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u8 ioeb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 moeb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } immed_ot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 omi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } index_ot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } op_encode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* PAACE Offsets 0x20-0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 reserved[8]; /* not currently implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* OME : Operation mapping entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * MOE : Mapped Operation Encodings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * The operation mapping table is table containing operation mapping entries (OME).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * The index of a particular OME is programmed in the PAACE entry for translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * in bound I/O operations corresponding to an LIODN. The OMT is used for translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * specifically in case of the indexed translation mode. Each OME contains a 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * byte mapped operation encoding (MOE), where each byte represents an MOE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define NUM_MOE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct ome {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 moe[NUM_MOE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PAACT_SIZE (sizeof(struct paace) * PAACE_NUMBER_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SPAACT_SIZE (sizeof(struct paace) * SPAACE_NUMBER_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OMT_SIZE (sizeof(struct ome) * OME_NUMBER_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PAMU_PAGE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PAMU_PAGE_SIZE 4096ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IOE_READ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IOE_READ_IDX 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IOE_WRITE 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IOE_WRITE_IDX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IOE_EREAD0 0x82 /* Enhanced read type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IOE_EREAD0_IDX 0x02 /* Enhanced read type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IOE_EWRITE0 0x83 /* Enhanced write type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IOE_EWRITE0_IDX 0x03 /* Enhanced write type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IOE_DIRECT0 0x84 /* Directive type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IOE_DIRECT0_IDX 0x04 /* Directive type 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IOE_EREAD1 0x85 /* Enhanced read type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IOE_EREAD1_IDX 0x05 /* Enhanced read type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IOE_EWRITE1 0x86 /* Enhanced write type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IOE_EWRITE1_IDX 0x06 /* Enhanced write type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IOE_DIRECT1 0x87 /* Directive type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IOE_DIRECT1_IDX 0x07 /* Directive type 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IOE_RAC 0x8c /* Read with Atomic clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IOE_RAC_IDX 0x0c /* Read with Atomic clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IOE_RAS 0x8d /* Read with Atomic set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IOE_RAS_IDX 0x0d /* Read with Atomic set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IOE_RAD 0x8e /* Read with Atomic decrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IOE_RAD_IDX 0x0e /* Read with Atomic decrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IOE_RAI 0x8f /* Read with Atomic increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IOE_RAI_IDX 0x0f /* Read with Atomic increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define EOE_READ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define EOE_WRITE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define EOE_RAC 0x0c /* Read with Atomic clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define EOE_RAS 0x0d /* Read with Atomic set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define EOE_RAD 0x0e /* Read with Atomic decrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define EOE_RAI 0x0f /* Read with Atomic increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define EOE_LDEC 0x10 /* Load external cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define EOE_LDECL 0x11 /* Load external cache with stash lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define EOE_LDECPE 0x12 /* Load external cache with preferred exclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define EOE_LDECPEL 0x13 /* Load external cache with preferred exclusive and lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define EOE_LDECFE 0x14 /* Load external cache with forced exclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define EOE_LDECFEL 0x15 /* Load external cache with forced exclusive and lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define EOE_RSA 0x16 /* Read with stash allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define EOE_RSAU 0x17 /* Read with stash allocate and unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define EOE_READI 0x18 /* Read with invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define EOE_RWNITC 0x19 /* Read with no intention to cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define EOE_WCI 0x1a /* Write cache inhibited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define EOE_WWSA 0x1b /* Write with stash allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define EOE_WWSAL 0x1c /* Write with stash allocate and lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define EOE_WWSAO 0x1d /* Write with stash allocate only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define EOE_WWSAOL 0x1e /* Write with stash allocate only and lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define EOE_VALID 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Function prototypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int pamu_domain_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int pamu_enable_liodn(int liodn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int pamu_disable_liodn(int liodn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void pamu_free_subwins(int liodn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 omi, unsigned long rpn, u32 snoopid, uint32_t stashid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 subwin_cnt, int prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) phys_addr_t subwin_size, u32 omi, unsigned long rpn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) uint32_t snoopid, u32 stashid, int enable, int prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 get_stash_id(u32 stash_dest_hint, u32 vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) void get_ome_index(u32 *omi_index, struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int pamu_update_paace_stash(int liodn, u32 subwin, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int pamu_disable_spaace(int liodn, u32 subwin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 pamu_get_max_subwin_cnt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #endif /* __FSL_PAMU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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