^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/adreno-smmu-priv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "arm-smmu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct qcom_smmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct arm_smmu_device smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) bool bypass_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u8 bypass_cbndx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int qcom_sdm845_smmu500_cfg_probe(struct arm_smmu_device *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 s2cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 smr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) for (i = 0; i < smmu->num_mapping_groups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) s2cr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_S2CR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (smmu->features & ARM_SMMU_FEAT_EXIDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) smmu->smrs[i].valid = FIELD_GET(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ARM_SMMU_S2CR_EXIDVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) s2cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) smmu->smrs[i].valid = FIELD_GET(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ARM_SMMU_SMR_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) smmu->s2crs[i].group = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) smmu->s2crs[i].count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) smmu->s2crs[i].type = FIELD_GET(ARM_SMMU_S2CR_TYPE, s2cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) smmu->s2crs[i].privcfg = FIELD_GET(ARM_SMMU_S2CR_PRIVCFG, s2cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) smmu->s2crs[i].cbndx = FIELD_GET(ARM_SMMU_S2CR_CBNDX, s2cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (!smmu->smrs[i].valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) smmu->s2crs[i].pinned = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) bitmap_set(smmu->context_map, smmu->s2crs[i].cbndx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QCOM_ADRENO_SMMU_GPU_SID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * The GPU will always use SID 0 so that is a handy way to uniquely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * identify it and configure it for per-instance pagetables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) for (i = 0; i < fwspec->num_ids; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (sid == QCOM_ADRENO_SMMU_GPU_SID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const void *cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct arm_smmu_domain *smmu_domain = (void *)cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct io_pgtable *pgtable =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return &pgtable->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Local implementation to configure TTBR0 with the specified pagetable config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * The GPU driver will call this to enable TTBR0 when per-instance pagetables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * are active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const struct io_pgtable_cfg *pgtbl_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct arm_smmu_domain *smmu_domain = (void *)cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* The domain must have split pagetables already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (cb->tcr[0] & ARM_SMMU_TCR_EPD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* If the pagetable config is NULL, disable TTBR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!pgtbl_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Do nothing if it is already disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Set TCR to the original configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 tcr = cb->tcr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Don't call this again if TTBR0 is already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tcr |= arm_smmu_lpae_tcr(pgtbl_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) cb->tcr[0] = tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct arm_smmu_device *smmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct device *dev, int start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Assign context bank 0 to the GPU device so the GPU hardware can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * switch pagetables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (qcom_adreno_smmu_is_gpu_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) start = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) count = smmu->num_context_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct adreno_smmu_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Only enable split pagetables for the GPU device (SID 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!qcom_adreno_smmu_is_gpu_device(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * All targets that use the qcom,adreno-smmu compatible string *should*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * be AARCH64 stage 1 but double check because the arm-smmu code assumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * that is the case when the TTBR1 quirk is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Initialize private interface with GPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) priv->cookie = smmu_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return container_of(smmu, struct qcom_smmu, smmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .compatible = "qcom,adreno" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .compatible = "qcom,mdp4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .compatible = "qcom,mdss" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .compatible = "qcom,sc7180-mdss" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .compatible = "qcom,sc7180-mss-pil" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .compatible = "qcom,sdm845-mdss" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "qcom,sdm845-mss-pil" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 smr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * With some firmware versions writes to S2CR of type FAULT are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * ignored, and writing BYPASS will end up written as FAULT in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * register. Perform a write to S2CR to detect if this is the case and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * if so reserve a context bank to emulate bypass streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) arm_smmu_gr0_write(smmu, last_s2cr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg = arm_smmu_gr0_read(smmu, last_s2cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) qsmmu->bypass_quirk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) set_bit(qsmmu->bypass_cbndx, smmu->context_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < smmu->num_mapping_groups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Ignore valid bit for SMR mask extraction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) smr &= ~ARM_SMMU_SMR_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) smmu->smrs[i].valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) smmu->s2crs[i].cbndx = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 cbndx = s2cr->cbndx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 type = s2cr->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (qsmmu->bypass_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (type == S2CR_TYPE_BYPASS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Firmware with quirky S2CR handling will substitute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * BYPASS writes with FAULT, so point the stream to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * reserved context bank and ask for translation on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) type = S2CR_TYPE_TRANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cbndx = qsmmu->bypass_cbndx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } else if (type == S2CR_TYPE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Firmware with quirky S2CR handling will ignore FAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * writes, so trick it to write FAULT by asking for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * BYPASS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) type = S2CR_TYPE_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cbndx = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, type) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FIELD_PREP(ARM_SMMU_S2CR_CBNDX, cbndx) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int qcom_smmu_def_domain_type(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const struct of_device_id *match =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) of_match_device(qcom_smmu_client_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return match ? IOMMU_DOMAIN_IDENTITY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * To address performance degradation in non-real time clients,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * such as USB and UFS, turn off wait-for-safe on sdm845 based boards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * such as MTP and db845, whose firmwares implement secure monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * call handlers to turn on/off the wait-for-safe logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = qcom_scm_qsmmu500_wait_safe_toggle(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) const struct device_node *np = smmu->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) arm_mmu500_reset(smmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return qcom_sdm845_smmu500_reset(smmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct arm_smmu_impl qcom_smmu_impl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .cfg_probe = qcom_smmu_cfg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .def_domain_type = qcom_smmu_def_domain_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .cfg_probe = qcom_sdm845_smmu500_cfg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .reset = qcom_smmu500_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .write_s2cr = qcom_smmu_write_s2cr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct arm_smmu_impl qcom_adreno_smmu_impl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .init_context = qcom_adreno_smmu_init_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .def_domain_type = qcom_smmu_def_domain_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .reset = qcom_smmu500_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) const struct arm_smmu_impl *impl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct qcom_smmu *qsmmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Check to make sure qcom_scm has finished probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!qcom_scm_is_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) qsmmu = devm_kzalloc(smmu->dev, sizeof(*qsmmu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!qsmmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) qsmmu->smmu = *smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) qsmmu->smmu.impl = impl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) devm_kfree(smmu->dev, smmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return &qsmmu->smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return qcom_smmu_create(smmu, &qcom_smmu_impl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags