^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Implementation of the IOMMU SVA API for the ARM SMMUv3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "arm-smmu-v3.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "../../io-pgtable-arm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static DEFINE_MUTEX(sva_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Check if the CPU ASID is available on the SMMU side. If a private context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * descriptor is using it, try to replace it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static struct arm_smmu_ctx_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) arm_smmu_share_asid(struct mm_struct *mm, u16 asid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 new_asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct arm_smmu_ctx_desc *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct arm_smmu_device *smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct arm_smmu_domain *smmu_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) cd = xa_load(&arm_smmu_asid_xa, asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (!cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (cd->mm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (WARN_ON(cd->mm != mm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* All devices bound to this mm use the same cd struct. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) refcount_inc(&cd->refs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) smmu_domain = container_of(cd, struct arm_smmu_domain, s1_cfg.cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) smmu = smmu_domain->smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ret = xa_alloc(&arm_smmu_asid_xa, &new_asid, cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return ERR_PTR(-ENOSPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Race with unmap: TLB invalidations will start targeting the new ASID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * which isn't assigned yet. We'll do an invalidate-all on the old ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * later, so it doesn't matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cd->asid = new_asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Update ASID and invalidate CD in all associated masters. There will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * be some overlap between use of both ASIDs, until we invalidate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) arm_smmu_write_ctx_desc(smmu_domain, 0, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Invalidate TLB entries previously associated with that context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) arm_smmu_tlb_inv_asid(smmu, asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) xa_erase(&arm_smmu_asid_xa, asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct arm_smmu_ctx_desc *arm_smmu_alloc_shared_cd(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u16 asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u64 tcr, par, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct arm_smmu_ctx_desc *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct arm_smmu_ctx_desc *ret = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) asid = arm64_mm_context_get(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (!asid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ERR_PTR(-ESRCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cd = kzalloc(sizeof(*cd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!cd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) goto out_put_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) refcount_set(&cd->refs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mutex_lock(&arm_smmu_asid_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = arm_smmu_share_asid(mm, asid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mutex_unlock(&arm_smmu_asid_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto out_free_cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) err = xa_insert(&arm_smmu_asid_xa, asid, cd, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mutex_unlock(&arm_smmu_asid_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto out_free_asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - vabits_actual) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (PAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case SZ_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case SZ_16K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case SZ_64K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) goto out_free_asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) par = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cd->ttbr = virt_to_phys(mm->pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cd->tcr = tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * MAIR value is pretty much constant and global, so we can just get it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * from the current CPU register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cd->mair = read_sysreg(mair_el1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) cd->asid = asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cd->mm = mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) out_free_asid:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) arm_smmu_free_asid(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) out_free_cd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) kfree(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) out_put_context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) arm64_mm_context_put(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return err < 0 ? ERR_PTR(err) : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void arm_smmu_free_shared_cd(struct arm_smmu_ctx_desc *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (arm_smmu_free_asid(cd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Unpin ASID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) arm64_mm_context_put(cd->mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) kfree(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool arm_smmu_sva_supported(struct arm_smmu_device *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long reg, fld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long oas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long asid_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 feat_mask = ARM_SMMU_FEAT_BTM | ARM_SMMU_FEAT_COHERENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (vabits_actual == 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) feat_mask |= ARM_SMMU_FEAT_VAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if ((smmu->features & feat_mask) != feat_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!(smmu->pgsize_bitmap & PAGE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Get the smallest PA size of all CPUs (sanitized by cpufeature). We're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * not even pretending to support AArch32 here. Abort if the MMU outputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * addresses larger than what we support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) oas = id_aa64mmfr0_parange_to_phys_shift(fld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (smmu->oas < oas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* We can support bigger ASIDs than the CPU, but not smaller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_ASID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) asid_bits = fld ? 16 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (smmu->asid_bits < asid_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * See max_pinned_asids in arch/arm64/mm/context.c. The following is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * generally the maximum number of bindable processes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (arm64_kernel_unmapped_at_el0())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) asid_bits--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_dbg(smmu->dev, "%d shared contexts\n", (1 << asid_bits) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) num_possible_cpus() - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static bool arm_smmu_iopf_supported(struct arm_smmu_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool arm_smmu_master_sva_supported(struct arm_smmu_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!(master->smmu->features & ARM_SMMU_FEAT_SVA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* SSID and IOPF support are mandatory for the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return master->ssid_bits && arm_smmu_iopf_supported(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bool arm_smmu_master_sva_enabled(struct arm_smmu_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mutex_lock(&sva_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) enabled = master->sva_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mutex_unlock(&sva_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int arm_smmu_master_enable_sva(struct arm_smmu_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mutex_lock(&sva_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) master->sva_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mutex_unlock(&sva_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int arm_smmu_master_disable_sva(struct arm_smmu_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mutex_lock(&sva_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!list_empty(&master->bonds)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(master->dev, "cannot disable SVA, device is bound\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mutex_unlock(&sva_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) master->sva_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mutex_unlock(&sva_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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