^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm #define SM8250 interconnect IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DRIVERS_INTERCONNECT_QCOM_SM8250_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SM8250_A1NOC_SNOC_MAS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SM8250_A1NOC_SNOC_SLV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SM8250_A2NOC_SNOC_MAS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SM8250_A2NOC_SNOC_SLV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SM8250_MASTER_A1NOC_CFG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SM8250_MASTER_A2NOC_CFG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SM8250_MASTER_AMPSS_M0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SM8250_MASTER_CAMNOC_HF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SM8250_MASTER_CAMNOC_ICP 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SM8250_MASTER_CAMNOC_SF 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SM8250_MASTER_CNOC_A2NOC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SM8250_MASTER_CNOC_DC_NOC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SM8250_MASTER_CNOC_MNOC_CFG 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SM8250_MASTER_COMPUTE_NOC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SM8250_MASTER_CRYPTO_CORE_0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SM8250_MASTER_GEM_NOC_CFG 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SM8250_MASTER_GEM_NOC_SNOC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SM8250_MASTER_GIC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SM8250_MASTER_GPU_TCU 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SM8250_MASTER_GRAPHICS_3D 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SM8250_MASTER_IPA 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SM8250_MASTER_IPA_CORE 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SM8250_MASTER_LLCC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SM8250_MASTER_MDP_PORT0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SM8250_MASTER_MDP_PORT1 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SM8250_MASTER_MNOC_HF_MEM_NOC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SM8250_MASTER_MNOC_SF_MEM_NOC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SM8250_MASTER_NPU 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SM8250_MASTER_NPU_CDP 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SM8250_MASTER_NPU_NOC_CFG 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SM8250_MASTER_NPU_SYS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SM8250_MASTER_PCIE 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SM8250_MASTER_PCIE_1 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SM8250_MASTER_PCIE_2 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SM8250_MASTER_PIMEM 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SM8250_MASTER_QDSS_BAM 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SM8250_MASTER_QDSS_DAP 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SM8250_MASTER_QDSS_ETR 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SM8250_MASTER_QSPI_0 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SM8250_MASTER_QUP_0 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SM8250_MASTER_QUP_1 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SM8250_MASTER_QUP_2 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SM8250_MASTER_ROTATOR 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SM8250_MASTER_SDCC_2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SM8250_MASTER_SDCC_4 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SM8250_MASTER_SNOC_CFG 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SM8250_MASTER_SNOC_GC_MEM_NOC 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SM8250_MASTER_SNOC_SF_MEM_NOC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SM8250_MASTER_SYS_TCU 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SM8250_MASTER_TSIF 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SM8250_MASTER_UFS_CARD 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SM8250_MASTER_UFS_MEM 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SM8250_MASTER_USB3 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SM8250_MASTER_USB3_1 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SM8250_MASTER_VIDEO_P0 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SM8250_MASTER_VIDEO_P1 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SM8250_MASTER_VIDEO_PROC 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SM8250_SLAVE_A1NOC_CFG 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SM8250_SLAVE_A2NOC_CFG 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SM8250_SLAVE_AHB2PHY_NORTH 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SM8250_SLAVE_AHB2PHY_SOUTH 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SM8250_SLAVE_AOSS 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SM8250_SLAVE_APPSS 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SM8250_SLAVE_CAMERA_CFG 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SM8250_SLAVE_CDSP_CFG 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SM8250_SLAVE_CDSP_MEM_NOC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SM8250_SLAVE_CLK_CTL 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SM8250_SLAVE_CNOC_A2NOC 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SM8250_SLAVE_CNOC_DDRSS 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SM8250_SLAVE_CNOC_MNOC_CFG 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SM8250_SLAVE_CRYPTO_0_CFG 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SM8250_SLAVE_CX_RDPM 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SM8250_SLAVE_DCC_CFG 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SM8250_SLAVE_DISPLAY_CFG 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SM8250_SLAVE_EBI_CH0 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SM8250_SLAVE_GEM_NOC_CFG 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SM8250_SLAVE_GEM_NOC_SNOC 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SM8250_SLAVE_GRAPHICS_3D_CFG 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SM8250_SLAVE_IMEM_CFG 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SM8250_SLAVE_IPA_CFG 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SM8250_SLAVE_IPA_CORE 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SM8250_SLAVE_IPC_ROUTER_CFG 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SM8250_SLAVE_ISENSE_CFG 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SM8250_SLAVE_LLCC 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SM8250_SLAVE_LLCC_CFG 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SM8250_SLAVE_LPASS 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SM8250_SLAVE_MNOC_HF_MEM_NOC 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SM8250_SLAVE_MNOC_SF_MEM_NOC 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SM8250_SLAVE_NPU_CAL_DP0 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SM8250_SLAVE_NPU_CAL_DP1 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SM8250_SLAVE_NPU_CFG 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SM8250_SLAVE_NPU_COMPUTE_NOC 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SM8250_SLAVE_NPU_CP 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SM8250_SLAVE_NPU_DPM 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SM8250_SLAVE_NPU_LLM_CFG 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SM8250_SLAVE_NPU_TCM 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SM8250_SLAVE_OCIMEM 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SM8250_SLAVE_PCIE_0 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SM8250_SLAVE_PCIE_0_CFG 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SM8250_SLAVE_PCIE_1 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SM8250_SLAVE_PCIE_1_CFG 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SM8250_SLAVE_PCIE_2 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SM8250_SLAVE_PCIE_2_CFG 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SM8250_SLAVE_PDM 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SM8250_SLAVE_PIMEM 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SM8250_SLAVE_PIMEM_CFG 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SM8250_SLAVE_PRNG 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SM8250_SLAVE_QDSS_CFG 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SM8250_SLAVE_QDSS_STM 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SM8250_SLAVE_QSPI_0 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SM8250_SLAVE_QUP_0 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SM8250_SLAVE_QUP_1 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SM8250_SLAVE_QUP_2 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SM8250_SLAVE_RBCPR_CX_CFG 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SM8250_SLAVE_RBCPR_MMCX_CFG 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SM8250_SLAVE_RBCPR_MX_CFG 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SM8250_SLAVE_SDCC_2 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SM8250_SLAVE_SDCC_4 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SM8250_SLAVE_SERVICE_A1NOC 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SM8250_SLAVE_SERVICE_A2NOC 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SM8250_SLAVE_SERVICE_CNOC 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SM8250_SLAVE_SERVICE_GEM_NOC 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SM8250_SLAVE_SERVICE_GEM_NOC_1 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SM8250_SLAVE_SERVICE_GEM_NOC_2 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SM8250_SLAVE_SERVICE_MNOC 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SM8250_SLAVE_SERVICE_NPU_NOC 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SM8250_SLAVE_SERVICE_SNOC 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SM8250_SLAVE_SNOC_CFG 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SM8250_SLAVE_SNOC_GEM_NOC_GC 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SM8250_SLAVE_SNOC_GEM_NOC_SF 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SM8250_SLAVE_TCSR 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SM8250_SLAVE_TCU 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SM8250_SLAVE_TLMM_NORTH 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SM8250_SLAVE_TLMM_SOUTH 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SM8250_SLAVE_TLMM_WEST 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SM8250_SLAVE_TSIF 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SM8250_SLAVE_UFS_CARD_CFG 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SM8250_SLAVE_UFS_MEM_CFG 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SM8250_SLAVE_USB3 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SM8250_SLAVE_USB3_1 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SM8250_SLAVE_VENUS_CFG 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SM8250_SLAVE_VSENSE_CTRL_CFG 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SM8250_SNOC_CNOC_MAS 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SM8250_SNOC_CNOC_SLV 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SM8250_MASTER_EPSS_L3_APPS 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SM8250_SLAVE_EPSS_L3 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags