^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interconnect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/interconnect/qcom,sm8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "bcm-voter.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "icc-rpmh.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sm8250.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) &bcm_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) &bcm_sn12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct qcom_icc_node *aggre1_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [MASTER_QSPI_0] = &qhm_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [MASTER_QUP_1] = &qhm_qup1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [MASTER_QUP_2] = &qhm_qup2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [MASTER_TSIF] = &qhm_tsif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [MASTER_PCIE_2] = &xm_pcie3_modem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [MASTER_SDCC_4] = &xm_sdc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [MASTER_UFS_MEM] = &xm_ufs_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [MASTER_USB3] = &xm_usb3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [MASTER_USB3_1] = &xm_usb3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct qcom_icc_desc sm8250_aggre1_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .nodes = aggre1_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .bcms = aggre1_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) &bcm_ce0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) &bcm_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) &bcm_sn12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct qcom_icc_node *aggre2_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [MASTER_QDSS_BAM] = &qhm_qdss_bam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [MASTER_QUP_0] = &qhm_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [MASTER_CNOC_A2NOC] = &qnm_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [MASTER_IPA] = &qxm_ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [MASTER_PCIE] = &xm_pcie3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [MASTER_PCIE_1] = &xm_pcie3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [MASTER_QDSS_ETR] = &xm_qdss_etr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [MASTER_SDCC_2] = &xm_sdc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [MASTER_UFS_CARD] = &xm_ufs_card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct qcom_icc_desc sm8250_aggre2_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .nodes = aggre2_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .bcms = aggre2_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct qcom_icc_bcm *compute_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) &bcm_co0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) &bcm_co2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct qcom_icc_node *compute_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [MASTER_NPU] = &qnm_npu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct qcom_icc_desc sm8250_compute_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .nodes = compute_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .num_nodes = ARRAY_SIZE(compute_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .bcms = compute_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .num_bcms = ARRAY_SIZE(compute_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct qcom_icc_bcm *config_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) &bcm_cn0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct qcom_icc_node *config_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [SNOC_CNOC_MAS] = &qnm_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [MASTER_QDSS_DAP] = &xm_qdss_dap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [SLAVE_AOSS] = &qhs_aoss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [SLAVE_CLK_CTL] = &qhs_clk_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [SLAVE_IPA_CFG] = &qhs_ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [SLAVE_LPASS] = &qhs_lpass_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [SLAVE_NPU_CFG] = &qhs_npu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [SLAVE_PDM] = &qhs_pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [SLAVE_PRNG] = &qhs_prng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [SLAVE_QSPI_0] = &qhs_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [SLAVE_QUP_0] = &qhs_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [SLAVE_QUP_1] = &qhs_qup1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [SLAVE_QUP_2] = &qhs_qup2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [SLAVE_SDCC_2] = &qhs_sdc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [SLAVE_SDCC_4] = &qhs_sdc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [SLAVE_TCSR] = &qhs_tcsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [SLAVE_TLMM_NORTH] = &qhs_tlmm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [SLAVE_TLMM_SOUTH] = &qhs_tlmm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [SLAVE_TLMM_WEST] = &qhs_tlmm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [SLAVE_TSIF] = &qhs_tsif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [SLAVE_USB3] = &qhs_usb3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [SLAVE_USB3_1] = &qhs_usb3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct qcom_icc_desc sm8250_config_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .nodes = config_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .num_nodes = ARRAY_SIZE(config_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .bcms = config_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .num_bcms = ARRAY_SIZE(config_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct qcom_icc_bcm *dc_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct qcom_icc_node *dc_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [SLAVE_LLCC_CFG] = &qhs_llcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct qcom_icc_desc sm8250_dc_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .nodes = dc_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .num_nodes = ARRAY_SIZE(dc_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .bcms = dc_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .num_bcms = ARRAY_SIZE(dc_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct qcom_icc_bcm *gem_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) &bcm_sh0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) &bcm_sh2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) &bcm_sh3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) &bcm_sh4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct qcom_icc_node *gem_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [MASTER_GPU_TCU] = &alm_gpu_tcu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [MASTER_SYS_TCU] = &alm_sys_tcu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [MASTER_AMPSS_M0] = &chm_apps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) [MASTER_GRAPHICS_3D] = &qnm_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [SLAVE_LLCC] = &qns_llcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct qcom_icc_desc sm8250_gem_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .nodes = gem_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .num_nodes = ARRAY_SIZE(gem_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .bcms = gem_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .num_bcms = ARRAY_SIZE(gem_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct qcom_icc_bcm *ipa_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) &bcm_ip0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct qcom_icc_node *ipa_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) [MASTER_IPA_CORE] = &ipa_core_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [SLAVE_IPA_CORE] = &ipa_core_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct qcom_icc_desc sm8250_ipa_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .nodes = ipa_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .bcms = ipa_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct qcom_icc_bcm *mc_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) &bcm_acv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &bcm_mc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct qcom_icc_node *mc_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [MASTER_LLCC] = &llcc_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [SLAVE_EBI_CH0] = &ebi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct qcom_icc_desc sm8250_mc_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .nodes = mc_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .num_nodes = ARRAY_SIZE(mc_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .bcms = mc_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .num_bcms = ARRAY_SIZE(mc_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct qcom_icc_bcm *mmss_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) &bcm_mm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &bcm_mm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) &bcm_mm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &bcm_mm3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct qcom_icc_node *mmss_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) [MASTER_VIDEO_P0] = &qnm_video0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) [MASTER_VIDEO_P1] = &qnm_video1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [MASTER_VIDEO_PROC] = &qnm_video_cvp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [MASTER_MDP_PORT0] = &qxm_mdp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [MASTER_MDP_PORT1] = &qxm_mdp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [MASTER_ROTATOR] = &qxm_rot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct qcom_icc_desc sm8250_mmss_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .nodes = mmss_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .bcms = mmss_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static struct qcom_icc_bcm *npu_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct qcom_icc_node *npu_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [MASTER_NPU_SYS] = &amm_npu_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) [MASTER_NPU_NOC_CFG] = &qhm_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) [SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [SLAVE_NPU_CP] = &qhs_cp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) [SLAVE_NPU_DPM] = &qhs_dpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) [SLAVE_ISENSE_CFG] = &qhs_isense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [SLAVE_NPU_LLM_CFG] = &qhs_llm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [SLAVE_NPU_TCM] = &qhs_tcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct qcom_icc_desc sm8250_npu_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .nodes = npu_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .num_nodes = ARRAY_SIZE(npu_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .bcms = npu_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .num_bcms = ARRAY_SIZE(npu_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct qcom_icc_bcm *system_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) &bcm_sn0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) &bcm_sn1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) &bcm_sn11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &bcm_sn2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &bcm_sn3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &bcm_sn4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &bcm_sn5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &bcm_sn6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &bcm_sn7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &bcm_sn8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &bcm_sn9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static struct qcom_icc_node *system_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [MASTER_PIMEM] = &qxm_pimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) [MASTER_GIC] = &xm_gic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) [SLAVE_APPSS] = &qhs_apss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) [SNOC_CNOC_SLV] = &qns_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [SLAVE_OCIMEM] = &qxs_imem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [SLAVE_PIMEM] = &qxs_pimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) [SLAVE_SERVICE_SNOC] = &srvc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) [SLAVE_PCIE_0] = &xs_pcie_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [SLAVE_PCIE_1] = &xs_pcie_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [SLAVE_PCIE_2] = &xs_pcie_modem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) [SLAVE_QDSS_STM] = &xs_qdss_stm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) [SLAVE_TCU] = &xs_sys_tcu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct qcom_icc_desc sm8250_system_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .nodes = system_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .num_nodes = ARRAY_SIZE(system_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .bcms = system_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .num_bcms = ARRAY_SIZE(system_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int qnoc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const struct qcom_icc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct icc_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct qcom_icc_node **qnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct qcom_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct icc_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) size_t num_nodes, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) desc = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) qnodes = desc->nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) num_nodes = desc->num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) provider = &qp->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) provider->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) provider->set = qcom_icc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) provider->pre_aggregate = qcom_icc_pre_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) provider->aggregate = qcom_icc_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) provider->xlate = of_icc_xlate_onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) INIT_LIST_HEAD(&provider->nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) provider->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) qp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) qp->bcms = desc->bcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) qp->num_bcms = desc->num_bcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) qp->voter = of_bcm_voter_get(qp->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (IS_ERR(qp->voter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return PTR_ERR(qp->voter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = icc_provider_add(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev_err(&pdev->dev, "error adding interconnect provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (i = 0; i < qp->num_bcms; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) for (i = 0; i < num_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) size_t j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!qnodes[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) node = icc_node_create(qnodes[i]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (IS_ERR(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = PTR_ERR(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) node->name = qnodes[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) node->data = qnodes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) icc_node_add(node, provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) for (j = 0; j < qnodes[i]->num_links; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) icc_link_create(node, qnodes[i]->links[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) data->nodes[i] = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) data->num_nodes = num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) platform_set_drvdata(pdev, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) icc_nodes_remove(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) icc_provider_del(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int qnoc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) icc_nodes_remove(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return icc_provider_del(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const struct of_device_id qnoc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { .compatible = "qcom,sm8250-aggre1-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .data = &sm8250_aggre1_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { .compatible = "qcom,sm8250-aggre2-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .data = &sm8250_aggre2_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { .compatible = "qcom,sm8250-compute-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .data = &sm8250_compute_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { .compatible = "qcom,sm8250-config-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .data = &sm8250_config_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { .compatible = "qcom,sm8250-dc-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .data = &sm8250_dc_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { .compatible = "qcom,sm8250-gem-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .data = &sm8250_gem_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { .compatible = "qcom,sm8250-ipa-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .data = &sm8250_ipa_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { .compatible = "qcom,sm8250-mc-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .data = &sm8250_mc_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { .compatible = "qcom,sm8250-mmss-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .data = &sm8250_mmss_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .compatible = "qcom,sm8250-npu-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .data = &sm8250_npu_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { .compatible = "qcom,sm8250-system-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .data = &sm8250_system_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MODULE_DEVICE_TABLE(of, qnoc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static struct platform_driver qnoc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .probe = qnoc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .remove = qnoc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .name = "qnoc-sm8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .of_match_table = qnoc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .sync_state = icc_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) module_platform_driver(qnoc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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