^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interconnect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/interconnect/qcom,sm8150.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "bcm-voter.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "icc-rpmh.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sm8150.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) &bcm_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &bcm_sn3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct qcom_icc_node *aggre1_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [MASTER_QUP_0] = &qhm_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [MASTER_EMAC] = &xm_emac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [MASTER_UFS_MEM] = &xm_ufs_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [MASTER_USB3] = &xm_usb3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [MASTER_USB3_1] = &xm_usb3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct qcom_icc_desc sm8150_aggre1_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .nodes = aggre1_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .bcms = aggre1_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) &bcm_ce0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) &bcm_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) &bcm_sn14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &bcm_sn3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct qcom_icc_node *aggre2_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [MASTER_QDSS_BAM] = &qhm_qdss_bam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [MASTER_QSPI] = &qhm_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [MASTER_QUP_1] = &qhm_qup1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [MASTER_QUP_2] = &qhm_qup2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [MASTER_TSIF] = &qhm_tsif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [MASTER_CNOC_A2NOC] = &qnm_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [MASTER_IPA] = &qxm_ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [MASTER_PCIE] = &xm_pcie3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [MASTER_PCIE_1] = &xm_pcie3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [MASTER_QDSS_ETR] = &xm_qdss_etr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [MASTER_SDCC_2] = &xm_sdc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [MASTER_SDCC_4] = &xm_sdc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct qcom_icc_desc sm8150_aggre2_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .nodes = aggre2_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .bcms = aggre2_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &bcm_mm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct qcom_icc_node *camnoc_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct qcom_icc_desc sm8150_camnoc_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .nodes = camnoc_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .bcms = camnoc_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct qcom_icc_bcm *compute_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) &bcm_co0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) &bcm_co1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct qcom_icc_node *compute_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [MASTER_NPU] = &qnm_npu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct qcom_icc_desc sm8150_compute_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .nodes = compute_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .num_nodes = ARRAY_SIZE(compute_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .bcms = compute_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .num_bcms = ARRAY_SIZE(compute_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct qcom_icc_bcm *config_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) &bcm_cn0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct qcom_icc_node *config_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [MASTER_SPDM] = &qhm_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [SNOC_CNOC_MAS] = &qnm_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [MASTER_QDSS_DAP] = &xm_qdss_dap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [SLAVE_AOP] = &qhs_aop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [SLAVE_AOSS] = &qhs_aoss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [SLAVE_CLK_CTL] = &qhs_clk_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [SLAVE_GLM] = &qhs_glm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [SLAVE_IPA_CFG] = &qhs_ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [SLAVE_NPU_CFG] = &qhs_npu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [SLAVE_PRNG] = &qhs_prng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [SLAVE_QSPI] = &qhs_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [SLAVE_QUP_2] = &qhs_qupv3_east,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [SLAVE_QUP_1] = &qhs_qupv3_north,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [SLAVE_QUP_0] = &qhs_qupv3_south,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [SLAVE_SDCC_2] = &qhs_sdc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [SLAVE_SDCC_4] = &qhs_sdc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [SLAVE_SSC_CFG] = &qhs_ssc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [SLAVE_TCSR] = &qhs_tcsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [SLAVE_TLMM_EAST] = &qhs_tlmm_east,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [SLAVE_TSIF] = &qhs_tsif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [SLAVE_USB3] = &qhs_usb3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [SLAVE_USB3_1] = &qhs_usb3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static struct qcom_icc_desc sm8150_config_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .nodes = config_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .num_nodes = ARRAY_SIZE(config_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .bcms = config_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .num_bcms = ARRAY_SIZE(config_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct qcom_icc_bcm *dc_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct qcom_icc_node *dc_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [SLAVE_LLCC_CFG] = &qhs_llcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct qcom_icc_desc sm8150_dc_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .nodes = dc_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .num_nodes = ARRAY_SIZE(dc_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .bcms = dc_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .num_bcms = ARRAY_SIZE(dc_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static struct qcom_icc_bcm *gem_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) &bcm_sh0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) &bcm_sh2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) &bcm_sh3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) &bcm_sh4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) &bcm_sh5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct qcom_icc_node *gem_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [MASTER_AMPSS_M0] = &acm_apps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [MASTER_GPU_TCU] = &acm_gpu_tcu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [MASTER_SYS_TCU] = &acm_sys_tcu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [MASTER_GRAPHICS_3D] = &qnm_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [MASTER_ECC] = &qxm_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) [SLAVE_ECC] = &qns_ecc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [SLAVE_LLCC] = &qns_llcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct qcom_icc_desc sm8150_gem_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .nodes = gem_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .num_nodes = ARRAY_SIZE(gem_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .bcms = gem_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .num_bcms = ARRAY_SIZE(gem_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct qcom_icc_bcm *ipa_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) &bcm_ip0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct qcom_icc_node *ipa_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [MASTER_IPA_CORE] = &ipa_core_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [SLAVE_IPA_CORE] = &ipa_core_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct qcom_icc_desc sm8150_ipa_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .nodes = ipa_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .bcms = ipa_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct qcom_icc_bcm *mc_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &bcm_acv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) &bcm_mc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct qcom_icc_node *mc_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [MASTER_LLCC] = &llcc_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [SLAVE_EBI_CH0] = &ebi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct qcom_icc_desc sm8150_mc_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .nodes = mc_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .num_nodes = ARRAY_SIZE(mc_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .bcms = mc_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .num_bcms = ARRAY_SIZE(mc_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct qcom_icc_bcm *mmss_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &bcm_mm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &bcm_mm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &bcm_mm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &bcm_mm3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct qcom_icc_node *mmss_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [MASTER_MDP_PORT0] = &qxm_mdp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) [MASTER_MDP_PORT1] = &qxm_mdp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [MASTER_ROTATOR] = &qxm_rot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [MASTER_VIDEO_P0] = &qxm_venus0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [MASTER_VIDEO_P1] = &qxm_venus1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static struct qcom_icc_desc sm8150_mmss_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .nodes = mmss_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .bcms = mmss_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static struct qcom_icc_bcm *system_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) &bcm_sn0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) &bcm_sn1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) &bcm_sn11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &bcm_sn12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &bcm_sn15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) &bcm_sn2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &bcm_sn3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &bcm_sn4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &bcm_sn5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) &bcm_sn8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &bcm_sn9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct qcom_icc_node *system_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [MASTER_PIMEM] = &qxm_pimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [MASTER_GIC] = &xm_gic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [SLAVE_APPSS] = &qhs_apss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [SNOC_CNOC_SLV] = &qns_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [SLAVE_OCIMEM] = &qxs_imem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [SLAVE_PIMEM] = &qxs_pimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [SLAVE_SERVICE_SNOC] = &srvc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [SLAVE_PCIE_0] = &xs_pcie_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [SLAVE_PCIE_1] = &xs_pcie_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [SLAVE_QDSS_STM] = &xs_qdss_stm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [SLAVE_TCU] = &xs_sys_tcu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static struct qcom_icc_desc sm8150_system_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .nodes = system_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .num_nodes = ARRAY_SIZE(system_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .bcms = system_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .num_bcms = ARRAY_SIZE(system_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int qnoc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const struct qcom_icc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct icc_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct qcom_icc_node **qnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct qcom_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct icc_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) size_t num_nodes, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) desc = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) qnodes = desc->nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) num_nodes = desc->num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) provider = &qp->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) provider->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) provider->set = qcom_icc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) provider->pre_aggregate = qcom_icc_pre_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) provider->aggregate = qcom_icc_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) provider->xlate = of_icc_xlate_onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) INIT_LIST_HEAD(&provider->nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) provider->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) qp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) qp->bcms = desc->bcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) qp->num_bcms = desc->num_bcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) qp->voter = of_bcm_voter_get(qp->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (IS_ERR(qp->voter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return PTR_ERR(qp->voter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = icc_provider_add(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(&pdev->dev, "error adding interconnect provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for (i = 0; i < qp->num_bcms; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) for (i = 0; i < num_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) size_t j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!qnodes[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) node = icc_node_create(qnodes[i]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (IS_ERR(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = PTR_ERR(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) node->name = qnodes[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) node->data = qnodes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) icc_node_add(node, provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) for (j = 0; j < qnodes[i]->num_links; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) icc_link_create(node, qnodes[i]->links[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) data->nodes[i] = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) data->num_nodes = num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) platform_set_drvdata(pdev, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) icc_nodes_remove(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) icc_provider_del(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int qnoc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) icc_nodes_remove(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return icc_provider_del(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const struct of_device_id qnoc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { .compatible = "qcom,sm8150-aggre1-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .data = &sm8150_aggre1_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { .compatible = "qcom,sm8150-aggre2-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .data = &sm8150_aggre2_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { .compatible = "qcom,sm8150-camnoc-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .data = &sm8150_camnoc_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { .compatible = "qcom,sm8150-compute-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .data = &sm8150_compute_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { .compatible = "qcom,sm8150-config-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .data = &sm8150_config_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { .compatible = "qcom,sm8150-dc-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .data = &sm8150_dc_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { .compatible = "qcom,sm8150-gem-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .data = &sm8150_gem_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { .compatible = "qcom,sm8150-ipa-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .data = &sm8150_ipa_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { .compatible = "qcom,sm8150-mc-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .data = &sm8150_mc_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { .compatible = "qcom,sm8150-mmss-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .data = &sm8150_mmss_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { .compatible = "qcom,sm8150-system-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .data = &sm8150_system_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MODULE_DEVICE_TABLE(of, qnoc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct platform_driver qnoc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .probe = qnoc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .remove = qnoc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .name = "qnoc-sm8150",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .of_match_table = qnoc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .sync_state = icc_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) module_platform_driver(qnoc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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