^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SDM845_MASTER_A1NOC_CFG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SDM845_MASTER_BLSP_1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SDM845_MASTER_TSIF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SDM845_MASTER_SDCC_2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SDM845_MASTER_SDCC_4 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SDM845_MASTER_UFS_CARD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SDM845_MASTER_UFS_MEM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SDM845_MASTER_PCIE_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SDM845_MASTER_A2NOC_CFG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SDM845_MASTER_QDSS_BAM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SDM845_MASTER_BLSP_2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SDM845_MASTER_CNOC_A2NOC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SDM845_MASTER_CRYPTO 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SDM845_MASTER_IPA 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SDM845_MASTER_PCIE_1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SDM845_MASTER_QDSS_ETR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SDM845_MASTER_USB3_0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SDM845_MASTER_USB3_1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SDM845_MASTER_CAMNOC_SF_UNCOMP 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SDM845_MASTER_SPDM 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDM845_MASTER_TIC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SDM845_MASTER_SNOC_CNOC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SDM845_MASTER_QDSS_DAP 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDM845_MASTER_CNOC_DC_NOC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SDM845_MASTER_APPSS_PROC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDM845_MASTER_GNOC_CFG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SDM845_MASTER_LLCC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SDM845_MASTER_TCU_0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDM845_MASTER_MEM_NOC_CFG 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SDM845_MASTER_GNOC_MEM_NOC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SDM845_MASTER_MNOC_HF_MEM_NOC 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDM845_MASTER_MNOC_SF_MEM_NOC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDM845_MASTER_SNOC_GC_MEM_NOC 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDM845_MASTER_SNOC_SF_MEM_NOC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SDM845_MASTER_GFX3D 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDM845_MASTER_CNOC_MNOC_CFG 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SDM845_MASTER_CAMNOC_HF0 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDM845_MASTER_CAMNOC_HF1 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDM845_MASTER_CAMNOC_SF 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDM845_MASTER_MDP0 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SDM845_MASTER_MDP1 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDM845_MASTER_ROTATOR 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDM845_MASTER_VIDEO_P0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDM845_MASTER_VIDEO_P1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDM845_MASTER_VIDEO_PROC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDM845_MASTER_SNOC_CFG 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDM845_MASTER_A1NOC_SNOC 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SDM845_MASTER_A2NOC_SNOC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDM845_MASTER_GNOC_SNOC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDM845_MASTER_MEM_NOC_SNOC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SDM845_MASTER_ANOC_PCIE_SNOC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDM845_MASTER_PIMEM 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDM845_MASTER_GIC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDM845_SLAVE_A1NOC_SNOC 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDM845_SLAVE_SERVICE_A1NOC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDM845_SLAVE_A2NOC_SNOC 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SDM845_SLAVE_ANOC_PCIE_SNOC 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDM845_SLAVE_SERVICE_A2NOC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDM845_SLAVE_CAMNOC_UNCOMP 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDM845_SLAVE_A1NOC_CFG 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDM845_SLAVE_A2NOC_CFG 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDM845_SLAVE_AOP 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SDM845_SLAVE_AOSS 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SDM845_SLAVE_CAMERA_CFG 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SDM845_SLAVE_CLK_CTL 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SDM845_SLAVE_CDSP_CFG 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SDM845_SLAVE_RBCPR_CX_CFG 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SDM845_SLAVE_CRYPTO_0_CFG 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SDM845_SLAVE_DCC_CFG 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SDM845_SLAVE_CNOC_DDRSS 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SDM845_SLAVE_DISPLAY_CFG 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SDM845_SLAVE_GLM 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SDM845_SLAVE_GFX3D_CFG 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SDM845_SLAVE_IMEM_CFG 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SDM845_SLAVE_IPA_CFG 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SDM845_SLAVE_CNOC_MNOC_CFG 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SDM845_SLAVE_PCIE_0_CFG 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SDM845_SLAVE_PCIE_1_CFG 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SDM845_SLAVE_PDM 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SDM845_SLAVE_SOUTH_PHY_CFG 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SDM845_SLAVE_PIMEM_CFG 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SDM845_SLAVE_PRNG 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SDM845_SLAVE_QDSS_CFG 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SDM845_SLAVE_BLSP_2 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SDM845_SLAVE_BLSP_1 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SDM845_SLAVE_SDCC_2 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SDM845_SLAVE_SDCC_4 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SDM845_SLAVE_SNOC_CFG 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SDM845_SLAVE_SPDM_WRAPPER 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SDM845_SLAVE_SPSS_CFG 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SDM845_SLAVE_TCSR 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SDM845_SLAVE_TLMM_NORTH 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SDM845_SLAVE_TLMM_SOUTH 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SDM845_SLAVE_TSIF 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SDM845_SLAVE_UFS_CARD_CFG 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SDM845_SLAVE_UFS_MEM_CFG 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SDM845_SLAVE_USB3_0 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SDM845_SLAVE_USB3_1 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SDM845_SLAVE_VENUS_CFG 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SDM845_SLAVE_VSENSE_CTRL_CFG 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SDM845_SLAVE_CNOC_A2NOC 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SDM845_SLAVE_SERVICE_CNOC 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SDM845_SLAVE_LLCC_CFG 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SDM845_SLAVE_MEM_NOC_CFG 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SDM845_SLAVE_GNOC_SNOC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SDM845_SLAVE_GNOC_MEM_NOC 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDM845_SLAVE_SERVICE_GNOC 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SDM845_SLAVE_EBI1 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDM845_SLAVE_MEM_NOC_GNOC 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SDM845_SLAVE_LLCC 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SDM845_SLAVE_MEM_NOC_SNOC 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SDM845_SLAVE_SERVICE_MEM_NOC 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SDM845_SLAVE_MNOC_SF_MEM_NOC 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SDM845_SLAVE_MNOC_HF_MEM_NOC 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SDM845_SLAVE_SERVICE_MNOC 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SDM845_SLAVE_APPSS 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SDM845_SLAVE_SNOC_CNOC 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SDM845_SLAVE_SNOC_MEM_NOC_GC 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SDM845_SLAVE_SNOC_MEM_NOC_SF 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDM845_SLAVE_IMEM 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SDM845_SLAVE_PCIE_0 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SDM845_SLAVE_PCIE_1 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SDM845_SLAVE_PIMEM 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SDM845_SLAVE_SERVICE_SNOC 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SDM845_SLAVE_QDSS_STM 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SDM845_SLAVE_TCU 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SDM845_MASTER_OSM_L3_APPS 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SDM845_SLAVE_OSM_L3 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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