^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interconnect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/interconnect/qcom,sdm845.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "bcm-voter.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "icc-rpmh.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sdm845.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DEFINE_QNODE(qhm_tsif, SDM845_MASTER_TSIF, 1, 4, SDM845_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DEFINE_QNODE(xm_sdc2, SDM845_MASTER_SDCC_2, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DEFINE_QNODE(xm_sdc4, SDM845_MASTER_SDCC_4, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DEFINE_QNODE(xm_ufs_card, SDM845_MASTER_UFS_CARD, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DEFINE_QNODE(xm_ufs_mem, SDM845_MASTER_UFS_MEM, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DEFINE_QNODE(xm_pcie_0, SDM845_MASTER_PCIE_0, 1, 8, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_QNODE(qhm_a2noc_cfg, SDM845_MASTER_A2NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_QNODE(qhm_qdss_bam, SDM845_MASTER_QDSS_BAM, 1, 4, SDM845_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_QNODE(qhm_qup2, SDM845_MASTER_BLSP_2, 1, 4, SDM845_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_QNODE(qnm_cnoc, SDM845_MASTER_CNOC_A2NOC, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_QNODE(qxm_crypto, SDM845_MASTER_CRYPTO, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_QNODE(qxm_ipa, SDM845_MASTER_IPA, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_QNODE(xm_pcie3_1, SDM845_MASTER_PCIE_1, 1, 8, SDM845_SLAVE_ANOC_PCIE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_QNODE(xm_qdss_etr, SDM845_MASTER_QDSS_ETR, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_QNODE(xm_usb3_0, SDM845_MASTER_USB3_0, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_QNODE(xm_usb3_1, SDM845_MASTER_USB3_1, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM845_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM845_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM845_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_QNODE(qhm_spdm, SDM845_MASTER_SPDM, 1, 4, SDM845_SLAVE_CNOC_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_QNODE(qhm_tic, SDM845_MASTER_TIC, 1, 4, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_QNODE(qnm_snoc, SDM845_MASTER_SNOC_CNOC, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_SERVICE_CNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_QNODE(xm_qdss_dap, SDM845_MASTER_QDSS_DAP, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_QNODE(qhm_cnoc, SDM845_MASTER_CNOC_DC_NOC, 1, 4, SDM845_SLAVE_LLCC_CFG, SDM845_SLAVE_MEM_NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_QNODE(acm_l3, SDM845_MASTER_APPSS_PROC, 1, 16, SDM845_SLAVE_GNOC_SNOC, SDM845_SLAVE_GNOC_MEM_NOC, SDM845_SLAVE_SERVICE_GNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_QNODE(pm_gnoc_cfg, SDM845_MASTER_GNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_GNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_QNODE(llcc_mc, SDM845_MASTER_LLCC, 4, 4, SDM845_SLAVE_EBI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_QNODE(acm_tcu, SDM845_MASTER_TCU_0, 1, 8, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_QNODE(qhm_memnoc_cfg, SDM845_MASTER_MEM_NOC_CFG, 1, 4, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, SDM845_SLAVE_SERVICE_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_QNODE(qnm_apps, SDM845_MASTER_GNOC_MEM_NOC, 2, 32, SDM845_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_QNODE(qnm_mnoc_hf, SDM845_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_QNODE(qnm_mnoc_sf, SDM845_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_QNODE(qnm_snoc_gc, SDM845_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM845_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEFINE_QNODE(qnm_snoc_sf, SDM845_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEFINE_QNODE(qxm_gpu, SDM845_MASTER_GFX3D, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_QNODE(qhm_mnoc_cfg, SDM845_MASTER_CNOC_MNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_MNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_QNODE(qxm_camnoc_hf0, SDM845_MASTER_CAMNOC_HF0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_QNODE(qxm_camnoc_hf1, SDM845_MASTER_CAMNOC_HF1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEFINE_QNODE(qxm_camnoc_sf, SDM845_MASTER_CAMNOC_SF, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_QNODE(qxm_mdp0, SDM845_MASTER_MDP0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_QNODE(qxm_mdp1, SDM845_MASTER_MDP1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_QNODE(qxm_rot, SDM845_MASTER_ROTATOR, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_QNODE(qxm_venus0, SDM845_MASTER_VIDEO_P0, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEFINE_QNODE(qxm_venus1, SDM845_MASTER_VIDEO_P1, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEFINE_QNODE(qxm_venus_arm9, SDM845_MASTER_VIDEO_PROC, 1, 8, SDM845_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_QNODE(qhm_snoc_cfg, SDM845_MASTER_SNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_QNODE(qnm_aggre1_noc, SDM845_MASTER_A1NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE_QNODE(qnm_aggre2_noc, SDM845_MASTER_A2NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEFINE_QNODE(qnm_gladiator_sodv, SDM845_MASTER_GNOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEFINE_QNODE(qnm_memnoc, SDM845_MASTER_MEM_NOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEFINE_QNODE(qnm_pcie_anoc, SDM845_MASTER_ANOC_PCIE_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_QDSS_STM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DEFINE_QNODE(qxm_pimem, SDM845_MASTER_PIMEM, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEFINE_QNODE(xm_gic, SDM845_MASTER_GIC, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEFINE_QNODE(qns_a1noc_snoc, SDM845_SLAVE_A1NOC_SNOC, 1, 16, SDM845_MASTER_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEFINE_QNODE(srvc_aggre1_noc, SDM845_SLAVE_SERVICE_A1NOC, 1, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE_QNODE(qns_pcie_a1noc_snoc, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEFINE_QNODE(qns_a2noc_snoc, SDM845_SLAVE_A2NOC_SNOC, 1, 16, SDM845_MASTER_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE_QNODE(qns_pcie_snoc, SDM845_SLAVE_ANOC_PCIE_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEFINE_QNODE(srvc_aggre2_noc, SDM845_SLAVE_SERVICE_A2NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE_QNODE(qns_camnoc_uncomp, SDM845_SLAVE_CAMNOC_UNCOMP, 1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEFINE_QNODE(qhs_a1_noc_cfg, SDM845_SLAVE_A1NOC_CFG, 1, 4, SDM845_MASTER_A1NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DEFINE_QNODE(qhs_a2_noc_cfg, SDM845_SLAVE_A2NOC_CFG, 1, 4, SDM845_MASTER_A2NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEFINE_QNODE(qhs_aop, SDM845_SLAVE_AOP, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEFINE_QNODE(qhs_aoss, SDM845_SLAVE_AOSS, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEFINE_QNODE(qhs_camera_cfg, SDM845_SLAVE_CAMERA_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEFINE_QNODE(qhs_clk_ctl, SDM845_SLAVE_CLK_CTL, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEFINE_QNODE(qhs_compute_dsp_cfg, SDM845_SLAVE_CDSP_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEFINE_QNODE(qhs_cpr_cx, SDM845_SLAVE_RBCPR_CX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEFINE_QNODE(qhs_crypto0_cfg, SDM845_SLAVE_CRYPTO_0_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEFINE_QNODE(qhs_dcc_cfg, SDM845_SLAVE_DCC_CFG, 1, 4, SDM845_MASTER_CNOC_DC_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEFINE_QNODE(qhs_ddrss_cfg, SDM845_SLAVE_CNOC_DDRSS, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEFINE_QNODE(qhs_display_cfg, SDM845_SLAVE_DISPLAY_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DEFINE_QNODE(qhs_glm, SDM845_SLAVE_GLM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEFINE_QNODE(qhs_gpuss_cfg, SDM845_SLAVE_GFX3D_CFG, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEFINE_QNODE(qhs_imem_cfg, SDM845_SLAVE_IMEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEFINE_QNODE(qhs_ipa, SDM845_SLAVE_IPA_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEFINE_QNODE(qhs_mnoc_cfg, SDM845_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM845_MASTER_CNOC_MNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DEFINE_QNODE(qhs_pcie0_cfg, SDM845_SLAVE_PCIE_0_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DEFINE_QNODE(qhs_pcie_gen3_cfg, SDM845_SLAVE_PCIE_1_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DEFINE_QNODE(qhs_pdm, SDM845_SLAVE_PDM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DEFINE_QNODE(qhs_phy_refgen_south, SDM845_SLAVE_SOUTH_PHY_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEFINE_QNODE(qhs_pimem_cfg, SDM845_SLAVE_PIMEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEFINE_QNODE(qhs_prng, SDM845_SLAVE_PRNG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEFINE_QNODE(qhs_qdss_cfg, SDM845_SLAVE_QDSS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEFINE_QNODE(qhs_qupv3_north, SDM845_SLAVE_BLSP_2, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEFINE_QNODE(qhs_qupv3_south, SDM845_SLAVE_BLSP_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEFINE_QNODE(qhs_sdc2, SDM845_SLAVE_SDCC_2, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEFINE_QNODE(qhs_sdc4, SDM845_SLAVE_SDCC_4, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEFINE_QNODE(qhs_snoc_cfg, SDM845_SLAVE_SNOC_CFG, 1, 4, SDM845_MASTER_SNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEFINE_QNODE(qhs_spdm, SDM845_SLAVE_SPDM_WRAPPER, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEFINE_QNODE(qhs_spss_cfg, SDM845_SLAVE_SPSS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DEFINE_QNODE(qhs_tcsr, SDM845_SLAVE_TCSR, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DEFINE_QNODE(qhs_tlmm_north, SDM845_SLAVE_TLMM_NORTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEFINE_QNODE(qhs_tlmm_south, SDM845_SLAVE_TLMM_SOUTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEFINE_QNODE(qhs_tsif, SDM845_SLAVE_TSIF, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEFINE_QNODE(qhs_ufs_card_cfg, SDM845_SLAVE_UFS_CARD_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEFINE_QNODE(qhs_ufs_mem_cfg, SDM845_SLAVE_UFS_MEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEFINE_QNODE(qhs_usb3_0, SDM845_SLAVE_USB3_0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEFINE_QNODE(qhs_usb3_1, SDM845_SLAVE_USB3_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEFINE_QNODE(qhs_venus_cfg, SDM845_SLAVE_VENUS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM845_SLAVE_VSENSE_CTRL_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DEFINE_QNODE(qns_cnoc_a2noc, SDM845_SLAVE_CNOC_A2NOC, 1, 8, SDM845_MASTER_CNOC_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEFINE_QNODE(srvc_cnoc, SDM845_SLAVE_SERVICE_CNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DEFINE_QNODE(qhs_llcc, SDM845_SLAVE_LLCC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEFINE_QNODE(qhs_memnoc, SDM845_SLAVE_MEM_NOC_CFG, 1, 4, SDM845_MASTER_MEM_NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEFINE_QNODE(qns_gladiator_sodv, SDM845_SLAVE_GNOC_SNOC, 1, 8, SDM845_MASTER_GNOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEFINE_QNODE(qns_gnoc_memnoc, SDM845_SLAVE_GNOC_MEM_NOC, 2, 32, SDM845_MASTER_GNOC_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEFINE_QNODE(srvc_gnoc, SDM845_SLAVE_SERVICE_GNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEFINE_QNODE(ebi, SDM845_SLAVE_EBI1, 4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEFINE_QNODE(qns_apps_io, SDM845_SLAVE_MEM_NOC_GNOC, 1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEFINE_QNODE(qns_llcc, SDM845_SLAVE_LLCC, 4, 16, SDM845_MASTER_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEFINE_QNODE(qns_memnoc_snoc, SDM845_SLAVE_MEM_NOC_SNOC, 1, 8, SDM845_MASTER_MEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEFINE_QNODE(srvc_memnoc, SDM845_SLAVE_SERVICE_MEM_NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEFINE_QNODE(qns2_mem_noc, SDM845_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM845_MASTER_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEFINE_QNODE(qns_mem_noc_hf, SDM845_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM845_MASTER_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEFINE_QNODE(srvc_mnoc, SDM845_SLAVE_SERVICE_MNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEFINE_QNODE(qhs_apss, SDM845_SLAVE_APPSS, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEFINE_QNODE(qns_cnoc, SDM845_SLAVE_SNOC_CNOC, 1, 8, SDM845_MASTER_SNOC_CNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEFINE_QNODE(qns_memnoc_gc, SDM845_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM845_MASTER_SNOC_GC_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEFINE_QNODE(qns_memnoc_sf, SDM845_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM845_MASTER_SNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEFINE_QNODE(qxs_imem, SDM845_SLAVE_IMEM, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEFINE_QNODE(qxs_pcie, SDM845_SLAVE_PCIE_0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEFINE_QNODE(qxs_pcie_gen3, SDM845_SLAVE_PCIE_1, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEFINE_QNODE(qxs_pimem, SDM845_SLAVE_PIMEM, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEFINE_QNODE(srvc_snoc, SDM845_SLAVE_SERVICE_SNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEFINE_QNODE(xs_qdss_stm, SDM845_SLAVE_QDSS_STM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEFINE_QNODE(xs_sys_tcu_cfg, SDM845_SLAVE_TCU, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &bcm_sn9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct qcom_icc_node *aggre1_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [MASTER_TSIF] = &qhm_tsif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [MASTER_SDCC_2] = &xm_sdc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [MASTER_SDCC_4] = &xm_sdc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [MASTER_UFS_CARD] = &xm_ufs_card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [MASTER_UFS_MEM] = &xm_ufs_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [MASTER_PCIE_0] = &xm_pcie_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct qcom_icc_desc sdm845_aggre1_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .nodes = aggre1_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .bcms = aggre1_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) &bcm_ce0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &bcm_sn11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) &bcm_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct qcom_icc_node *aggre2_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [MASTER_QDSS_BAM] = &qhm_qdss_bam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [MASTER_CNOC_A2NOC] = &qnm_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [MASTER_CRYPTO] = &qxm_crypto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [MASTER_IPA] = &qxm_ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [MASTER_PCIE_1] = &xm_pcie3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [MASTER_QDSS_ETR] = &xm_qdss_etr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [MASTER_USB3_0] = &xm_usb3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [MASTER_USB3_1] = &xm_usb3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct qcom_icc_desc sdm845_aggre2_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .nodes = aggre2_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .bcms = aggre2_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct qcom_icc_bcm *config_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) &bcm_cn0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct qcom_icc_node *config_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [MASTER_SPDM] = &qhm_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [MASTER_TIC] = &qhm_tic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [MASTER_SNOC_CNOC] = &qnm_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [MASTER_QDSS_DAP] = &xm_qdss_dap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [SLAVE_AOP] = &qhs_aop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [SLAVE_AOSS] = &qhs_aoss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [SLAVE_CLK_CTL] = &qhs_clk_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [SLAVE_GLM] = &qhs_glm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [SLAVE_IPA_CFG] = &qhs_ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [SLAVE_PDM] = &qhs_pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [SLAVE_PRNG] = &qhs_prng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [SLAVE_BLSP_2] = &qhs_qupv3_north,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [SLAVE_BLSP_1] = &qhs_qupv3_south,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [SLAVE_SDCC_2] = &qhs_sdc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) [SLAVE_SDCC_4] = &qhs_sdc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [SLAVE_TCSR] = &qhs_tcsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [SLAVE_TSIF] = &qhs_tsif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [SLAVE_USB3_0] = &qhs_usb3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [SLAVE_USB3_1] = &qhs_usb3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct qcom_icc_desc sdm845_config_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .nodes = config_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .num_nodes = ARRAY_SIZE(config_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .bcms = config_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .num_bcms = ARRAY_SIZE(config_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct qcom_icc_bcm *dc_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct qcom_icc_node *dc_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [MASTER_CNOC_DC_NOC] = &qhm_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [SLAVE_LLCC_CFG] = &qhs_llcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct qcom_icc_desc sdm845_dc_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .nodes = dc_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .num_nodes = ARRAY_SIZE(dc_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .bcms = dc_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .num_bcms = ARRAY_SIZE(dc_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct qcom_icc_bcm *gladiator_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct qcom_icc_node *gladiator_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [MASTER_APPSS_PROC] = &acm_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [MASTER_GNOC_CFG] = &pm_gnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [SLAVE_SERVICE_GNOC] = &srvc_gnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct qcom_icc_desc sdm845_gladiator_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .nodes = gladiator_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .bcms = gladiator_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct qcom_icc_bcm *mem_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) &bcm_mc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) &bcm_acv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) &bcm_sh0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) &bcm_sh1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) &bcm_sh2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &bcm_sh3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) &bcm_sh5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct qcom_icc_node *mem_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [MASTER_TCU_0] = &acm_tcu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [MASTER_GNOC_MEM_NOC] = &qnm_apps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [MASTER_GFX3D] = &qxm_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [SLAVE_LLCC] = &qns_llcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [MASTER_LLCC] = &llcc_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [SLAVE_EBI1] = &ebi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct qcom_icc_desc sdm845_mem_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .nodes = mem_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .num_nodes = ARRAY_SIZE(mem_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .bcms = mem_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .num_bcms = ARRAY_SIZE(mem_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct qcom_icc_bcm *mmss_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) &bcm_mm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &bcm_mm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) &bcm_mm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) &bcm_mm3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct qcom_icc_node *mmss_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [MASTER_MDP0] = &qxm_mdp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [MASTER_MDP1] = &qxm_mdp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [MASTER_ROTATOR] = &qxm_rot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [MASTER_VIDEO_P0] = &qxm_venus0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [MASTER_VIDEO_P1] = &qxm_venus1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct qcom_icc_desc sdm845_mmss_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .nodes = mmss_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .bcms = mmss_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct qcom_icc_bcm *system_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) &bcm_sn0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) &bcm_sn1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) &bcm_sn2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) &bcm_sn3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) &bcm_sn4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) &bcm_sn5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) &bcm_sn6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) &bcm_sn7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) &bcm_sn8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) &bcm_sn9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) &bcm_sn11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) &bcm_sn12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &bcm_sn14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &bcm_sn15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct qcom_icc_node *system_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [MASTER_PIMEM] = &qxm_pimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [MASTER_GIC] = &xm_gic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [SLAVE_APPSS] = &qhs_apss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [SLAVE_SNOC_CNOC] = &qns_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [SLAVE_IMEM] = &qxs_imem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [SLAVE_PCIE_0] = &qxs_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [SLAVE_PCIE_1] = &qxs_pcie_gen3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [SLAVE_PIMEM] = &qxs_pimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [SLAVE_SERVICE_SNOC] = &srvc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [SLAVE_QDSS_STM] = &xs_qdss_stm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [SLAVE_TCU] = &xs_sys_tcu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct qcom_icc_desc sdm845_system_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .nodes = system_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .num_nodes = ARRAY_SIZE(system_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .bcms = system_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .num_bcms = ARRAY_SIZE(system_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int qnoc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) const struct qcom_icc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct icc_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct qcom_icc_node **qnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct qcom_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct icc_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) size_t num_nodes, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) desc = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) qnodes = desc->nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) num_nodes = desc->num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) data = devm_kzalloc(&pdev->dev, struct_size(data, nodes, num_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) provider = &qp->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) provider->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) provider->set = qcom_icc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) provider->pre_aggregate = qcom_icc_pre_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) provider->aggregate = qcom_icc_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) provider->xlate_extended = qcom_icc_xlate_extended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) INIT_LIST_HEAD(&provider->nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) provider->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) qp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) qp->bcms = desc->bcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) qp->num_bcms = desc->num_bcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) qp->voter = of_bcm_voter_get(qp->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (IS_ERR(qp->voter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(&pdev->dev, "bcm_voter err:%ld\n", PTR_ERR(qp->voter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return PTR_ERR(qp->voter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = icc_provider_add(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_err(&pdev->dev, "error adding interconnect provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) for (i = 0; i < qp->num_bcms; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 0; i < num_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) size_t j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!qnodes[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) node = icc_node_create(qnodes[i]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (IS_ERR(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = PTR_ERR(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) node->name = qnodes[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) node->data = qnodes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) icc_node_add(node, provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) for (j = 0; j < qnodes[i]->num_links; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) icc_link_create(node, qnodes[i]->links[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) data->nodes[i] = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) data->num_nodes = num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) platform_set_drvdata(pdev, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) icc_nodes_remove(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) icc_provider_del(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int qnoc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) icc_nodes_remove(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return icc_provider_del(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct of_device_id qnoc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .compatible = "qcom,sdm845-aggre1-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .data = &sdm845_aggre1_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .compatible = "qcom,sdm845-aggre2-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .data = &sdm845_aggre2_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .compatible = "qcom,sdm845-config-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .data = &sdm845_config_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { .compatible = "qcom,sdm845-dc-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .data = &sdm845_dc_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { .compatible = "qcom,sdm845-gladiator-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .data = &sdm845_gladiator_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { .compatible = "qcom,sdm845-mem-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .data = &sdm845_mem_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { .compatible = "qcom,sdm845-mmss-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .data = &sdm845_mmss_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { .compatible = "qcom,sdm845-system-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .data = &sdm845_system_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MODULE_DEVICE_TABLE(of, qnoc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct platform_driver qnoc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .probe = qnoc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .remove = qnoc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .name = "qnoc-sdm845",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .of_match_table = qnoc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .sync_state = icc_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) module_platform_driver(qnoc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_DESCRIPTION("Qualcomm sdm845 NoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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