^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Qualcomm #define SC7180 interconnect IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DRIVERS_INTERCONNECT_QCOM_SC7180_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DRIVERS_INTERCONNECT_QCOM_SC7180_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SC7180_MASTER_APPSS_PROC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SC7180_MASTER_SYS_TCU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SC7180_MASTER_NPU_SYS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SC7180_MASTER_IPA_CORE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SC7180_MASTER_LLCC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SC7180_MASTER_A1NOC_CFG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SC7180_MASTER_A2NOC_CFG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SC7180_MASTER_CNOC_DC_NOC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SC7180_MASTER_GEM_NOC_CFG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SC7180_MASTER_CNOC_MNOC_CFG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SC7180_MASTER_NPU_NOC_CFG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SC7180_MASTER_QDSS_BAM 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SC7180_MASTER_QSPI 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SC7180_MASTER_QUP_0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SC7180_MASTER_QUP_1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SC7180_MASTER_SNOC_CFG 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SC7180_MASTER_A1NOC_SNOC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SC7180_MASTER_A2NOC_SNOC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SC7180_MASTER_COMPUTE_NOC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SC7180_MASTER_GEM_NOC_SNOC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SC7180_MASTER_MNOC_HF_MEM_NOC 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SC7180_MASTER_MNOC_SF_MEM_NOC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SC7180_MASTER_NPU 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SC7180_MASTER_SNOC_CNOC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SC7180_MASTER_SNOC_GC_MEM_NOC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC7180_MASTER_SNOC_SF_MEM_NOC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC7180_MASTER_QUP_CORE_0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC7180_MASTER_QUP_CORE_1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC7180_MASTER_CAMNOC_HF0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SC7180_MASTER_CAMNOC_HF1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC7180_MASTER_CAMNOC_HF0_UNCOMP 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SC7180_MASTER_CAMNOC_HF1_UNCOMP 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC7180_MASTER_CAMNOC_SF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC7180_MASTER_CAMNOC_SF_UNCOMP 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC7180_MASTER_CRYPTO 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC7180_MASTER_GFX3D 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC7180_MASTER_IPA 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC7180_MASTER_MDP0 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC7180_MASTER_NPU_PROC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC7180_MASTER_PIMEM 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC7180_MASTER_ROTATOR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC7180_MASTER_VIDEO_P0 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC7180_MASTER_VIDEO_PROC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC7180_MASTER_QDSS_DAP 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC7180_MASTER_QDSS_ETR 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC7180_MASTER_SDCC_2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC7180_MASTER_UFS_MEM 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC7180_MASTER_USB3 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC7180_MASTER_EMMC 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC7180_SLAVE_EBI1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC7180_SLAVE_IPA_CORE 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC7180_SLAVE_A1NOC_CFG 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC7180_SLAVE_A2NOC_CFG 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC7180_SLAVE_AHB2PHY_SOUTH 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC7180_SLAVE_AHB2PHY_CENTER 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC7180_SLAVE_AOP 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC7180_SLAVE_AOSS 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC7180_SLAVE_APPSS 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC7180_SLAVE_BOOT_ROM 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC7180_SLAVE_NPU_CAL_DP0 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC7180_SLAVE_CAMERA_CFG 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC7180_SLAVE_CLK_CTL 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC7180_SLAVE_NPU_CP 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC7180_SLAVE_RBCPR_CX_CFG 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC7180_SLAVE_RBCPR_MX_CFG 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC7180_SLAVE_CRYPTO_0_CFG 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC7180_SLAVE_DCC_CFG 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC7180_SLAVE_CNOC_DDRSS 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC7180_SLAVE_DISPLAY_CFG 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC7180_SLAVE_DISPLAY_THROTTLE_CFG 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC7180_SLAVE_NPU_DPM 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC7180_SLAVE_EMMC_CFG 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC7180_SLAVE_GEM_NOC_CFG 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC7180_SLAVE_GLM 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SC7180_SLAVE_GFX3D_CFG 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SC7180_SLAVE_IMEM_CFG 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SC7180_SLAVE_IPA_CFG 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SC7180_SLAVE_ISENSE_CFG 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC7180_SLAVE_LLCC_CFG 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC7180_SLAVE_NPU_LLM_CFG 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SC7180_SLAVE_MSS_PROC_MS_MPU_CFG 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SC7180_SLAVE_CNOC_MNOC_CFG 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SC7180_SLAVE_CNOC_MSS 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC7180_SLAVE_NPU_CFG 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC7180_SLAVE_NPU_DMA_BWMON_CFG 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC7180_SLAVE_NPU_PROC_BWMON_CFG 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SC7180_SLAVE_PDM 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SC7180_SLAVE_PIMEM_CFG 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SC7180_SLAVE_PRNG 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SC7180_SLAVE_QDSS_CFG 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC7180_SLAVE_QM_CFG 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC7180_SLAVE_QM_MPU_CFG 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SC7180_SLAVE_QSPI_0 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SC7180_SLAVE_QUP_0 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SC7180_SLAVE_QUP_1 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SC7180_SLAVE_SDCC_2 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SC7180_SLAVE_SECURITY 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SC7180_SLAVE_SNOC_CFG 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SC7180_SLAVE_NPU_TCM 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SC7180_SLAVE_TCSR 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SC7180_SLAVE_TLMM_WEST 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SC7180_SLAVE_TLMM_NORTH 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SC7180_SLAVE_TLMM_SOUTH 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SC7180_SLAVE_UFS_MEM_CFG 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SC7180_SLAVE_USB3 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SC7180_SLAVE_VENUS_CFG 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SC7180_SLAVE_VENUS_THROTTLE_CFG 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SC7180_SLAVE_VSENSE_CTRL_CFG 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SC7180_SLAVE_A1NOC_SNOC 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SC7180_SLAVE_A2NOC_SNOC 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SC7180_SLAVE_CAMNOC_UNCOMP 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SC7180_SLAVE_CDSP_GEM_NOC 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SC7180_SLAVE_SNOC_CNOC 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SC7180_SLAVE_GEM_NOC_SNOC 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SC7180_SLAVE_SNOC_GEM_NOC_GC 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SC7180_SLAVE_SNOC_GEM_NOC_SF 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SC7180_SLAVE_LLCC 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SC7180_SLAVE_MNOC_HF_MEM_NOC 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SC7180_SLAVE_MNOC_SF_MEM_NOC 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SC7180_SLAVE_NPU_COMPUTE_NOC 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SC7180_SLAVE_QUP_CORE_0 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SC7180_SLAVE_QUP_CORE_1 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SC7180_SLAVE_IMEM 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SC7180_SLAVE_PIMEM 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SC7180_SLAVE_SERVICE_A1NOC 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SC7180_SLAVE_SERVICE_A2NOC 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SC7180_SLAVE_SERVICE_CNOC 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SC7180_SLAVE_SERVICE_GEM_NOC 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SC7180_SLAVE_SERVICE_MNOC 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SC7180_SLAVE_SERVICE_NPU_NOC 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SC7180_SLAVE_SERVICE_SNOC 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SC7180_SLAVE_QDSS_STM 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SC7180_SLAVE_TCU 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SC7180_MASTER_OSM_L3_APPS 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SC7180_SLAVE_OSM_L3 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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