^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interconnect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/interconnect/qcom,sc7180.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "bcm-voter.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "icc-rpmh.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sc7180.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_QNODE(ipa_core_master, SC7180_MASTER_IPA_CORE, 1, 8, SC7180_SLAVE_IPA_CORE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEFINE_QNODE(ipa_core_slave, SC7180_SLAVE_IPA_CORE, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &bcm_cn1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct qcom_icc_node *aggre1_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [MASTER_QSPI] = &qhm_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [MASTER_QUP_0] = &qhm_qup_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [MASTER_SDCC_2] = &xm_sdc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [MASTER_EMMC] = &xm_emmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [MASTER_UFS_MEM] = &xm_ufs_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct qcom_icc_desc sc7180_aggre1_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .nodes = aggre1_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .bcms = aggre1_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) &bcm_ce0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct qcom_icc_node *aggre2_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [MASTER_QDSS_BAM] = &qhm_qdss_bam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [MASTER_QUP_1] = &qhm_qup_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [MASTER_USB3] = &qhm_usb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [MASTER_CRYPTO] = &qxm_crypto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [MASTER_IPA] = &qxm_ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [MASTER_QDSS_ETR] = &xm_qdss_etr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct qcom_icc_desc sc7180_aggre2_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .nodes = aggre2_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .bcms = aggre2_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct qcom_icc_bcm *camnoc_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) &bcm_mm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct qcom_icc_node *camnoc_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct qcom_icc_desc sc7180_camnoc_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .nodes = camnoc_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .bcms = camnoc_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct qcom_icc_bcm *compute_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &bcm_co0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) &bcm_co2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &bcm_co3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct qcom_icc_node *compute_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [MASTER_NPU] = &qnm_npu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [MASTER_NPU_PROC] = &qxm_npu_dsp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct qcom_icc_desc sc7180_compute_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .nodes = compute_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .num_nodes = ARRAY_SIZE(compute_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .bcms = compute_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .num_bcms = ARRAY_SIZE(compute_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct qcom_icc_bcm *config_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) &bcm_cn0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) &bcm_cn1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct qcom_icc_node *config_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [MASTER_SNOC_CNOC] = &qnm_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [MASTER_QDSS_DAP] = &xm_qdss_dap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [SLAVE_AOP] = &qhs_aop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [SLAVE_AOSS] = &qhs_aoss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [SLAVE_BOOT_ROM] = &qhs_boot_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [SLAVE_CLK_CTL] = &qhs_clk_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [SLAVE_GLM] = &qhs_glm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [SLAVE_IPA_CFG] = &qhs_ipa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [SLAVE_NPU_CFG] = &qhs_npu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [SLAVE_PDM] = &qhs_pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [SLAVE_PRNG] = &qhs_prng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [SLAVE_QM_CFG] = &qhs_qm_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [SLAVE_QSPI_0] = &qhs_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [SLAVE_QUP_0] = &qhs_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [SLAVE_QUP_1] = &qhs_qup1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [SLAVE_SDCC_2] = &qhs_sdc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [SLAVE_SECURITY] = &qhs_security,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [SLAVE_TCSR] = &qhs_tcsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [SLAVE_TLMM_WEST] = &qhs_tlmm_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [SLAVE_USB3] = &qhs_usb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct qcom_icc_desc sc7180_config_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .nodes = config_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .num_nodes = ARRAY_SIZE(config_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .bcms = config_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .num_bcms = ARRAY_SIZE(config_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct qcom_icc_node *dc_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [SLAVE_LLCC_CFG] = &qhs_llcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct qcom_icc_desc sc7180_dc_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .nodes = dc_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .num_nodes = ARRAY_SIZE(dc_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct qcom_icc_bcm *gem_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &bcm_sh0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) &bcm_sh2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &bcm_sh3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &bcm_sh4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct qcom_icc_node *gem_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [MASTER_APPSS_PROC] = &acm_apps0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [MASTER_SYS_TCU] = &acm_sys_tcu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [MASTER_GFX3D] = &qxm_gpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [SLAVE_LLCC] = &qns_llcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct qcom_icc_desc sc7180_gem_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .nodes = gem_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .num_nodes = ARRAY_SIZE(gem_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .bcms = gem_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .num_bcms = ARRAY_SIZE(gem_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static struct qcom_icc_bcm *ipa_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) &bcm_ip0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct qcom_icc_node *ipa_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [MASTER_IPA_CORE] = &ipa_core_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [SLAVE_IPA_CORE] = &ipa_core_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct qcom_icc_desc sc7180_ipa_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .nodes = ipa_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .bcms = ipa_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct qcom_icc_bcm *mc_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) &bcm_acv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) &bcm_mc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct qcom_icc_node *mc_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [MASTER_LLCC] = &llcc_mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) [SLAVE_EBI1] = &ebi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct qcom_icc_desc sc7180_mc_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .nodes = mc_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .num_nodes = ARRAY_SIZE(mc_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .bcms = mc_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .num_bcms = ARRAY_SIZE(mc_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct qcom_icc_bcm *mmss_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) &bcm_mm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) &bcm_mm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &bcm_mm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct qcom_icc_node *mmss_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [MASTER_MDP0] = &qxm_mdp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [MASTER_ROTATOR] = &qxm_rot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [MASTER_VIDEO_P0] = &qxm_venus0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct qcom_icc_desc sc7180_mmss_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .nodes = mmss_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .bcms = mmss_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct qcom_icc_node *npu_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) [MASTER_NPU_SYS] = &amm_npu_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [SLAVE_NPU_CP] = &qhs_cp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [SLAVE_NPU_DPM] = &qhs_dpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [SLAVE_ISENSE_CFG] = &qhs_isense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [SLAVE_NPU_LLM_CFG] = &qhs_llm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [SLAVE_NPU_TCM] = &qhs_tcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct qcom_icc_desc sc7180_npu_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .nodes = npu_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .num_nodes = ARRAY_SIZE(npu_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct qcom_icc_bcm *qup_virt_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &bcm_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct qcom_icc_node *qup_virt_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) [MASTER_QUP_CORE_0] = &qup_core_master_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) [MASTER_QUP_CORE_1] = &qup_core_master_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [SLAVE_QUP_CORE_0] = &qup_core_slave_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [SLAVE_QUP_CORE_1] = &qup_core_slave_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct qcom_icc_desc sc7180_qup_virt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .nodes = qup_virt_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .num_nodes = ARRAY_SIZE(qup_virt_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .bcms = qup_virt_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .num_bcms = ARRAY_SIZE(qup_virt_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct qcom_icc_bcm *system_noc_bcms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &bcm_sn0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) &bcm_sn1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &bcm_sn2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) &bcm_sn3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &bcm_sn4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) &bcm_sn7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) &bcm_sn9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) &bcm_sn12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct qcom_icc_node *system_noc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [MASTER_PIMEM] = &qxm_pimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [SLAVE_APPSS] = &qhs_apss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [SLAVE_SNOC_CNOC] = &qns_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [SLAVE_IMEM] = &qxs_imem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [SLAVE_PIMEM] = &qxs_pimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [SLAVE_SERVICE_SNOC] = &srvc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [SLAVE_QDSS_STM] = &xs_qdss_stm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [SLAVE_TCU] = &xs_sys_tcu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct qcom_icc_desc sc7180_system_noc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .nodes = system_noc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .num_nodes = ARRAY_SIZE(system_noc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .bcms = system_noc_bcms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .num_bcms = ARRAY_SIZE(system_noc_bcms),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int qnoc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) const struct qcom_icc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct icc_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct qcom_icc_node **qnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct qcom_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct icc_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) size_t num_nodes, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) desc = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) qnodes = desc->nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) num_nodes = desc->num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) provider = &qp->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) provider->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) provider->set = qcom_icc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) provider->pre_aggregate = qcom_icc_pre_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) provider->aggregate = qcom_icc_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) provider->xlate_extended = qcom_icc_xlate_extended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) INIT_LIST_HEAD(&provider->nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) provider->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) qp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) qp->bcms = desc->bcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) qp->num_bcms = desc->num_bcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) qp->voter = of_bcm_voter_get(qp->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (IS_ERR(qp->voter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return PTR_ERR(qp->voter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = icc_provider_add(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(&pdev->dev, "error adding interconnect provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) for (i = 0; i < qp->num_bcms; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (i = 0; i < num_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) size_t j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!qnodes[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) node = icc_node_create(qnodes[i]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (IS_ERR(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = PTR_ERR(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) node->name = qnodes[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) node->data = qnodes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) icc_node_add(node, provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) for (j = 0; j < qnodes[i]->num_links; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) icc_link_create(node, qnodes[i]->links[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) data->nodes[i] = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) data->num_nodes = num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) platform_set_drvdata(pdev, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) icc_nodes_remove(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) icc_provider_del(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int qnoc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) icc_nodes_remove(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return icc_provider_del(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const struct of_device_id qnoc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { .compatible = "qcom,sc7180-aggre1-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .data = &sc7180_aggre1_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { .compatible = "qcom,sc7180-aggre2-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .data = &sc7180_aggre2_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { .compatible = "qcom,sc7180-camnoc-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .data = &sc7180_camnoc_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { .compatible = "qcom,sc7180-compute-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .data = &sc7180_compute_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { .compatible = "qcom,sc7180-config-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .data = &sc7180_config_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { .compatible = "qcom,sc7180-dc-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .data = &sc7180_dc_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { .compatible = "qcom,sc7180-gem-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .data = &sc7180_gem_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { .compatible = "qcom,sc7180-ipa-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .data = &sc7180_ipa_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { .compatible = "qcom,sc7180-mc-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .data = &sc7180_mc_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { .compatible = "qcom,sc7180-mmss-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .data = &sc7180_mmss_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { .compatible = "qcom,sc7180-npu-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .data = &sc7180_npu_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { .compatible = "qcom,sc7180-qup-virt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .data = &sc7180_qup_virt},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { .compatible = "qcom,sc7180-system-noc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .data = &sc7180_system_noc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_DEVICE_TABLE(of, qnoc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct platform_driver qnoc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .probe = qnoc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .remove = qnoc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .name = "qnoc-sc7180",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .of_match_table = qnoc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .sync_state = icc_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) module_platform_driver(qnoc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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