^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <dt-bindings/interconnect/qcom,qcs404.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "smd-rpm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RPM_BUS_MASTER_REQ 0x73616d62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RPM_BUS_SLAVE_REQ 0x766c7362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) QCS404_MASTER_AMPSS_M0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) QCS404_MASTER_GRAPHICS_3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) QCS404_MASTER_MDP_PORT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) QCS404_SNOC_BIMC_1_MAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) QCS404_MASTER_TCU_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) QCS404_MASTER_SPDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) QCS404_MASTER_BLSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) QCS404_MASTER_BLSP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) QCS404_MASTER_XM_USB_HS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) QCS404_MASTER_CRYPTO_CORE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) QCS404_MASTER_SDCC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) QCS404_MASTER_SDCC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) QCS404_SNOC_PNOC_MAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) QCS404_MASTER_QPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) QCS404_MASTER_QDSS_BAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) QCS404_BIMC_SNOC_MAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) QCS404_PNOC_SNOC_MAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) QCS404_MASTER_QDSS_ETR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) QCS404_MASTER_EMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) QCS404_MASTER_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) QCS404_MASTER_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) QCS404_PNOC_INT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) QCS404_PNOC_INT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) QCS404_PNOC_INT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) QCS404_PNOC_SLV_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) QCS404_PNOC_SLV_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) QCS404_PNOC_SLV_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) QCS404_PNOC_SLV_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) QCS404_PNOC_SLV_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) QCS404_PNOC_SLV_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) QCS404_PNOC_SLV_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) QCS404_PNOC_SLV_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) QCS404_PNOC_SLV_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) QCS404_PNOC_SLV_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) QCS404_PNOC_SLV_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) QCS404_SNOC_QDSS_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) QCS404_SNOC_INT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) QCS404_SNOC_INT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) QCS404_SNOC_INT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) QCS404_SLAVE_EBI_CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) QCS404_BIMC_SNOC_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) QCS404_SLAVE_SPDM_WRAPPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) QCS404_SLAVE_PDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) QCS404_SLAVE_PRNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) QCS404_SLAVE_TCSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) QCS404_SLAVE_SNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) QCS404_SLAVE_MESSAGE_RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) QCS404_SLAVE_DISPLAY_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) QCS404_SLAVE_GRAPHICS_3D_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) QCS404_SLAVE_BLSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) QCS404_SLAVE_TLMM_NORTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) QCS404_SLAVE_PCIE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) QCS404_SLAVE_EMAC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) QCS404_SLAVE_BLSP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) QCS404_SLAVE_TLMM_EAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) QCS404_SLAVE_TCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) QCS404_SLAVE_PMIC_ARB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) QCS404_SLAVE_SDCC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) QCS404_SLAVE_SDCC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) QCS404_SLAVE_TLMM_SOUTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) QCS404_SLAVE_USB_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) QCS404_SLAVE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) QCS404_SLAVE_CRYPTO_0_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) QCS404_PNOC_SNOC_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) QCS404_SLAVE_APPSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) QCS404_SLAVE_WCSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) QCS404_SNOC_BIMC_1_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) QCS404_SLAVE_OCIMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) QCS404_SNOC_PNOC_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) QCS404_SLAVE_QDSS_STM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) QCS404_SLAVE_CATS_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) QCS404_SLAVE_OCMEM_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) QCS404_SLAVE_LPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define to_qcom_provider(_provider) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) container_of(_provider, struct qcom_icc_provider, provider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct clk_bulk_data bus_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .id = "bus" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .id = "bus_a" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * struct qcom_icc_provider - Qualcomm specific interconnect provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @provider: generic interconnect provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @bus_clks: the clk_bulk_data table of bus clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @num_clks: the total number of clk_bulk_data entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct qcom_icc_provider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct icc_provider provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct clk_bulk_data *bus_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QCS404_MAX_LINKS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * struct qcom_icc_node - Qualcomm specific interconnect nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @name: the node name used in debugfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @id: a unique node identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @links: an array of nodes where we can go next while traversing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @num_links: the total number of @links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @buswidth: width of the interconnect between a node and the bus (bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @mas_rpm_id: RPM id for devices that are bus masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @slv_rpm_id: RPM id for devices that are bus slaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @rate: current bus clock rate in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct qcom_icc_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 links[QCS404_MAX_LINKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u16 num_links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int mas_rpm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int slv_rpm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct qcom_icc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct qcom_icc_node **nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) size_t num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct qcom_icc_node _name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .buswidth = _buswidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .mas_rpm_id = _mas_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .slv_rpm_id = _slv_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .links = { __VA_ARGS__ }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEFINE_QNODE(mas_snoc_bimc_1, QCS404_SNOC_BIMC_1_MAS, 8, 76, -1, QCS404_SLAVE_EBI_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEFINE_QNODE(mas_tcu_0, QCS404_MASTER_TCU_0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DEFINE_QNODE(mas_spdm, QCS404_MASTER_SPDM, 4, -1, -1, QCS404_PNOC_INT_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DEFINE_QNODE(mas_blsp_1, QCS404_MASTER_BLSP_1, 4, 41, -1, QCS404_PNOC_INT_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEFINE_QNODE(mas_blsp_2, QCS404_MASTER_BLSP_2, 4, 39, -1, QCS404_PNOC_INT_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEFINE_QNODE(mas_xi_usb_hs1, QCS404_MASTER_XM_USB_HS1, 8, 138, -1, QCS404_PNOC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DEFINE_QNODE(mas_crypto, QCS404_MASTER_CRYPTO_CORE0, 8, 23, -1, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DEFINE_QNODE(mas_sdcc_1, QCS404_MASTER_SDCC_1, 8, 33, -1, QCS404_PNOC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DEFINE_QNODE(mas_sdcc_2, QCS404_MASTER_SDCC_2, 8, 35, -1, QCS404_PNOC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE_QNODE(mas_snoc_pcnoc, QCS404_SNOC_PNOC_MAS, 8, 77, -1, QCS404_PNOC_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEFINE_QNODE(mas_qpic, QCS404_MASTER_QPIC, 4, -1, -1, QCS404_PNOC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEFINE_QNODE(mas_qdss_bam, QCS404_MASTER_QDSS_BAM, 4, -1, -1, QCS404_SNOC_QDSS_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEFINE_QNODE(mas_bimc_snoc, QCS404_BIMC_SNOC_MAS, 8, 21, -1, QCS404_SLAVE_OCMEM_64, QCS404_SLAVE_CATS_128, QCS404_SNOC_INT_0, QCS404_SNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFINE_QNODE(mas_pcnoc_snoc, QCS404_PNOC_SNOC_MAS, 8, 29, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_2, QCS404_SNOC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEFINE_QNODE(mas_qdss_etr, QCS404_MASTER_QDSS_ETR, 8, -1, -1, QCS404_SNOC_QDSS_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEFINE_QNODE(mas_emac, QCS404_MASTER_EMAC, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEFINE_QNODE(mas_pcie, QCS404_MASTER_PCIE, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEFINE_QNODE(mas_usb3, QCS404_MASTER_USB3, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEFINE_QNODE(pcnoc_int_0, QCS404_PNOC_INT_0, 8, 85, 114, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEFINE_QNODE(pcnoc_int_2, QCS404_PNOC_INT_2, 8, 124, 184, QCS404_PNOC_SLV_10, QCS404_SLAVE_TCU, QCS404_PNOC_SLV_11, QCS404_PNOC_SLV_2, QCS404_PNOC_SLV_3, QCS404_PNOC_SLV_0, QCS404_PNOC_SLV_1, QCS404_PNOC_SLV_6, QCS404_PNOC_SLV_7, QCS404_PNOC_SLV_4, QCS404_PNOC_SLV_8, QCS404_PNOC_SLV_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DEFINE_QNODE(pcnoc_int_3, QCS404_PNOC_INT_3, 8, 125, 185, QCS404_PNOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEFINE_QNODE(pcnoc_s_0, QCS404_PNOC_SLV_0, 4, 89, 118, QCS404_SLAVE_PRNG, QCS404_SLAVE_SPDM_WRAPPER, QCS404_SLAVE_PDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEFINE_QNODE(pcnoc_s_1, QCS404_PNOC_SLV_1, 4, 90, 119, QCS404_SLAVE_TCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEFINE_QNODE(pcnoc_s_2, QCS404_PNOC_SLV_2, 4, -1, -1, QCS404_SLAVE_GRAPHICS_3D_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DEFINE_QNODE(pcnoc_s_3, QCS404_PNOC_SLV_3, 4, 92, 121, QCS404_SLAVE_MESSAGE_RAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DEFINE_QNODE(pcnoc_s_4, QCS404_PNOC_SLV_4, 4, 93, 122, QCS404_SLAVE_SNOC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DEFINE_QNODE(pcnoc_s_6, QCS404_PNOC_SLV_6, 4, 94, 123, QCS404_SLAVE_BLSP_1, QCS404_SLAVE_TLMM_NORTH, QCS404_SLAVE_EMAC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DEFINE_QNODE(pcnoc_s_7, QCS404_PNOC_SLV_7, 4, 95, 124, QCS404_SLAVE_TLMM_SOUTH, QCS404_SLAVE_DISPLAY_CFG, QCS404_SLAVE_SDCC_1, QCS404_SLAVE_PCIE_1, QCS404_SLAVE_SDCC_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DEFINE_QNODE(pcnoc_s_8, QCS404_PNOC_SLV_8, 4, 96, 125, QCS404_SLAVE_CRYPTO_0_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DEFINE_QNODE(pcnoc_s_9, QCS404_PNOC_SLV_9, 4, 97, 126, QCS404_SLAVE_BLSP_2, QCS404_SLAVE_TLMM_EAST, QCS404_SLAVE_PMIC_ARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DEFINE_QNODE(pcnoc_s_10, QCS404_PNOC_SLV_10, 4, 157, -1, QCS404_SLAVE_USB_HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DEFINE_QNODE(pcnoc_s_11, QCS404_PNOC_SLV_11, 4, 158, 246, QCS404_SLAVE_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DEFINE_QNODE(qdss_int, QCS404_SNOC_QDSS_INT, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DEFINE_QNODE(snoc_int_0, QCS404_SNOC_INT_0, 8, 99, 130, QCS404_SLAVE_LPASS, QCS404_SLAVE_APPSS, QCS404_SLAVE_WCSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DEFINE_QNODE(snoc_int_1, QCS404_SNOC_INT_1, 8, 100, 131, QCS404_SNOC_PNOC_SLV, QCS404_SNOC_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DEFINE_QNODE(snoc_int_2, QCS404_SNOC_INT_2, 8, 134, 197, QCS404_SLAVE_QDSS_STM, QCS404_SLAVE_OCIMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DEFINE_QNODE(slv_ebi, QCS404_SLAVE_EBI_CH0, 8, -1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DEFINE_QNODE(slv_bimc_snoc, QCS404_BIMC_SNOC_SLV, 8, -1, 2, QCS404_BIMC_SNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DEFINE_QNODE(slv_spdm, QCS404_SLAVE_SPDM_WRAPPER, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DEFINE_QNODE(slv_pdm, QCS404_SLAVE_PDM, 4, -1, 41, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DEFINE_QNODE(slv_prng, QCS404_SLAVE_PRNG, 4, -1, 44, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DEFINE_QNODE(slv_tcsr, QCS404_SLAVE_TCSR, 4, -1, 50, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DEFINE_QNODE(slv_snoc_cfg, QCS404_SLAVE_SNOC_CFG, 4, -1, 70, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DEFINE_QNODE(slv_message_ram, QCS404_SLAVE_MESSAGE_RAM, 4, -1, 55, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DEFINE_QNODE(slv_disp_ss_cfg, QCS404_SLAVE_DISPLAY_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DEFINE_QNODE(slv_gpu_cfg, QCS404_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DEFINE_QNODE(slv_blsp_1, QCS404_SLAVE_BLSP_1, 4, -1, 39, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DEFINE_QNODE(slv_tlmm_north, QCS404_SLAVE_TLMM_NORTH, 4, -1, 214, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DEFINE_QNODE(slv_pcie, QCS404_SLAVE_PCIE_1, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DEFINE_QNODE(slv_ethernet, QCS404_SLAVE_EMAC_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DEFINE_QNODE(slv_blsp_2, QCS404_SLAVE_BLSP_2, 4, -1, 37, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DEFINE_QNODE(slv_tlmm_east, QCS404_SLAVE_TLMM_EAST, 4, -1, 213, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DEFINE_QNODE(slv_tcu, QCS404_SLAVE_TCU, 8, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DEFINE_QNODE(slv_pmic_arb, QCS404_SLAVE_PMIC_ARB, 4, -1, 59, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DEFINE_QNODE(slv_sdcc_1, QCS404_SLAVE_SDCC_1, 4, -1, 31, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DEFINE_QNODE(slv_sdcc_2, QCS404_SLAVE_SDCC_2, 4, -1, 33, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DEFINE_QNODE(slv_tlmm_south, QCS404_SLAVE_TLMM_SOUTH, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DEFINE_QNODE(slv_usb_hs, QCS404_SLAVE_USB_HS, 4, -1, 40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DEFINE_QNODE(slv_usb3, QCS404_SLAVE_USB3, 4, -1, 22, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DEFINE_QNODE(slv_crypto_0_cfg, QCS404_SLAVE_CRYPTO_0_CFG, 4, -1, 52, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DEFINE_QNODE(slv_pcnoc_snoc, QCS404_PNOC_SNOC_SLV, 8, -1, 45, QCS404_PNOC_SNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DEFINE_QNODE(slv_kpss_ahb, QCS404_SLAVE_APPSS, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DEFINE_QNODE(slv_wcss, QCS404_SLAVE_WCSS, 4, -1, 23, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DEFINE_QNODE(slv_snoc_bimc_1, QCS404_SNOC_BIMC_1_SLV, 8, -1, 104, QCS404_SNOC_BIMC_1_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DEFINE_QNODE(slv_imem, QCS404_SLAVE_OCIMEM, 8, -1, 26, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DEFINE_QNODE(slv_snoc_pcnoc, QCS404_SNOC_PNOC_SLV, 8, -1, 28, QCS404_SNOC_PNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DEFINE_QNODE(slv_qdss_stm, QCS404_SLAVE_QDSS_STM, 4, -1, 30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DEFINE_QNODE(slv_cats_0, QCS404_SLAVE_CATS_128, 16, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DEFINE_QNODE(slv_cats_1, QCS404_SLAVE_OCMEM_64, 8, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DEFINE_QNODE(slv_lpass, QCS404_SLAVE_LPASS, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct qcom_icc_node *qcs404_bimc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [MASTER_AMPSS_M0] = &mas_apps_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [MASTER_OXILI] = &mas_oxili,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [MASTER_MDP_PORT0] = &mas_mdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [MASTER_TCU_0] = &mas_tcu_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [SLAVE_EBI_CH0] = &slv_ebi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct qcom_icc_desc qcs404_bimc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .nodes = qcs404_bimc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct qcom_icc_node *qcs404_pcnoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [MASTER_SPDM] = &mas_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [MASTER_BLSP_1] = &mas_blsp_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [MASTER_BLSP_2] = &mas_blsp_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [MASTER_CRYPT0] = &mas_crypto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [MASTER_SDCC_1] = &mas_sdcc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [MASTER_SDCC_2] = &mas_sdcc_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [MASTER_QPIC] = &mas_qpic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [PCNOC_INT_0] = &pcnoc_int_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [PCNOC_INT_2] = &pcnoc_int_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [PCNOC_INT_3] = &pcnoc_int_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [PCNOC_S_0] = &pcnoc_s_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [PCNOC_S_1] = &pcnoc_s_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [PCNOC_S_2] = &pcnoc_s_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [PCNOC_S_3] = &pcnoc_s_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [PCNOC_S_4] = &pcnoc_s_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) [PCNOC_S_6] = &pcnoc_s_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [PCNOC_S_7] = &pcnoc_s_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [PCNOC_S_8] = &pcnoc_s_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [PCNOC_S_9] = &pcnoc_s_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [PCNOC_S_10] = &pcnoc_s_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [PCNOC_S_11] = &pcnoc_s_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [SLAVE_SPDM] = &slv_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [SLAVE_PDM] = &slv_pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [SLAVE_PRNG] = &slv_prng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [SLAVE_TCSR] = &slv_tcsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [SLAVE_MESSAGE_RAM] = &slv_message_ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [SLAVE_GPU_CFG] = &slv_gpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [SLAVE_BLSP_1] = &slv_blsp_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [SLAVE_BLSP_2] = &slv_blsp_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [SLAVE_PCIE] = &slv_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [SLAVE_ETHERNET] = &slv_ethernet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [SLAVE_TLMM_EAST] = &slv_tlmm_east,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [SLAVE_TCU] = &slv_tcu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [SLAVE_PMIC_ARB] = &slv_pmic_arb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [SLAVE_SDCC_1] = &slv_sdcc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [SLAVE_SDCC_2] = &slv_sdcc_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [SLAVE_USB_HS] = &slv_usb_hs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [SLAVE_USB3] = &slv_usb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct qcom_icc_desc qcs404_pcnoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .nodes = qcs404_pcnoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static struct qcom_icc_node *qcs404_snoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [MASTER_QDSS_BAM] = &mas_qdss_bam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [MASTER_QDSS_ETR] = &mas_qdss_etr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [MASTER_EMAC] = &mas_emac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [MASTER_PCIE] = &mas_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [MASTER_USB3] = &mas_usb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [QDSS_INT] = &qdss_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [SNOC_INT_0] = &snoc_int_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [SNOC_INT_1] = &snoc_int_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [SNOC_INT_2] = &snoc_int_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [SLAVE_KPSS_AHB] = &slv_kpss_ahb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [SLAVE_WCSS] = &slv_wcss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [SLAVE_IMEM] = &slv_imem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [SLAVE_QDSS_STM] = &slv_qdss_stm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [SLAVE_CATS_0] = &slv_cats_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [SLAVE_CATS_1] = &slv_cats_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [SLAVE_LPASS] = &slv_lpass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct qcom_icc_desc qcs404_snoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .nodes = qcs404_snoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct qcom_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct qcom_icc_node *qn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct icc_node *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u64 sum_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u64 max_peak_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 agg_avg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 agg_peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) qn = src->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) provider = src->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) qp = to_qcom_provider(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) list_for_each_entry(n, &provider->nodes, node_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &agg_avg, &agg_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) sum_bw = icc_units_to_bps(agg_avg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) max_peak_bw = icc_units_to_bps(agg_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* send bandwidth request message to the RPM processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (qn->mas_rpm_id != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RPM_BUS_MASTER_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) qn->mas_rpm_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sum_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) qn->mas_rpm_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (qn->slv_rpm_id != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) RPM_BUS_SLAVE_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) qn->slv_rpm_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) sum_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pr_err("qcom_icc_rpm_smd_send slv error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) rate = max(sum_bw, max_peak_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) do_div(rate, qn->buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (qn->rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) for (i = 0; i < qp->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = clk_set_rate(qp->bus_clks[i].clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pr_err("%s clk_set_rate error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) qp->bus_clks[i].id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) qn->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int qnoc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) const struct qcom_icc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct icc_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct qcom_icc_node **qnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct qcom_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct icc_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) size_t num_nodes, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* wait for the RPM proxy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!qcom_icc_rpm_smd_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) desc = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) qnodes = desc->nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) num_nodes = desc->num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!qp->bus_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) qp->num_clks = ARRAY_SIZE(bus_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) provider = &qp->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) INIT_LIST_HEAD(&provider->nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) provider->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) provider->set = qcom_icc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) provider->aggregate = icc_std_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) provider->xlate = of_icc_xlate_onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) provider->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = icc_provider_add(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(dev, "error adding interconnect provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) for (i = 0; i < num_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) size_t j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) node = icc_node_create(qnodes[i]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (IS_ERR(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = PTR_ERR(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) node->name = qnodes[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) node->data = qnodes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) icc_node_add(node, provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_dbg(dev, "registered node %s\n", node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* populate links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (j = 0; j < qnodes[i]->num_links; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) icc_link_create(node, qnodes[i]->links[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) data->nodes[i] = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) data->num_nodes = num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) platform_set_drvdata(pdev, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) icc_nodes_remove(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) icc_provider_del(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int qnoc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) icc_nodes_remove(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return icc_provider_del(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct of_device_id qcs404_noc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct platform_driver qcs404_noc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .probe = qnoc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .remove = qnoc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .name = "qnoc-qcs404",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .of_match_table = qcs404_noc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) module_platform_driver(qcs404_noc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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