Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <dt-bindings/interconnect/qcom,osm-l3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "sc7180.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "sdm845.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "sm8150.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "sm8250.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LUT_MAX_ENTRIES			40U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LUT_SRC				GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LUT_L_VAL			GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_HW_DIV			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* OSM Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_ENABLE			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OSM_LUT_ROW_SIZE		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OSM_REG_FREQ_LUT		0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OSM_REG_PERF_STATE		0x920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* EPSS Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define EPSS_LUT_ROW_SIZE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define EPSS_REG_FREQ_LUT		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EPSS_REG_PERF_STATE		0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OSM_L3_MAX_LINKS		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define to_qcom_provider(_provider) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct qcom_osm_l3_icc_provider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int max_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int reg_perf_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned long lut_tables[LUT_MAX_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct icc_provider provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * struct qcom_icc_node - Qualcomm specific interconnect nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @name: the node name used in debugfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @links: an array of nodes where we can go next while traversing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @id: a unique node identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * @num_links: the total number of @links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @buswidth: width of the interconnect between a node and the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct qcom_icc_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u16 links[OSM_L3_MAX_LINKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u16 num_links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u16 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct qcom_icc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	const struct qcom_icc_node **nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	size_t num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned int lut_row_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned int reg_freq_lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned int reg_perf_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DEFINE_QNODE(_name, _id, _buswidth, ...)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	static const struct qcom_icc_node _name = {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.name = #_name,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.id = _id,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.buswidth = _buswidth,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.links = { __VA_ARGS__ },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static const struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	[MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	[SLAVE_OSM_L3] = &sdm845_osm_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static const struct qcom_icc_desc sdm845_icc_osm_l3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.nodes = sdm845_osm_l3_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.lut_row_size = OSM_LUT_ROW_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.reg_freq_lut = OSM_REG_FREQ_LUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.reg_perf_state = OSM_REG_PERF_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	[SLAVE_OSM_L3] = &sc7180_osm_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct qcom_icc_desc sc7180_icc_osm_l3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.nodes = sc7180_osm_l3_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.lut_row_size = OSM_LUT_ROW_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.reg_freq_lut = OSM_REG_FREQ_LUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.reg_perf_state = OSM_REG_PERF_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct qcom_icc_node *sm8150_osm_l3_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	[SLAVE_OSM_L3] = &sm8150_osm_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.nodes = sm8150_osm_l3_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.lut_row_size = OSM_LUT_ROW_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.reg_freq_lut = OSM_REG_FREQ_LUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.reg_perf_state = OSM_REG_PERF_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct qcom_icc_node *sm8250_epss_l3_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	[MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	[SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct qcom_icc_desc sm8250_icc_epss_l3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.nodes = sm8250_epss_l3_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.lut_row_size = EPSS_LUT_ROW_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.reg_freq_lut = EPSS_REG_FREQ_LUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.reg_perf_state = EPSS_REG_PERF_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct qcom_osm_l3_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	const struct qcom_icc_node *qn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct icc_node *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 agg_peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32 agg_avg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	qn = src->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	provider = src->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	qp = to_qcom_provider(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	list_for_each_entry(n, &provider->nodes, node_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				    &agg_avg, &agg_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	rate = max(agg_avg, agg_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	rate = icc_units_to_bps(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	do_div(rate, qn->buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	for (index = 0; index < qp->max_state - 1; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		if (qp->lut_tables[index] >= rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	writel_relaxed(index, qp->base + qp->reg_perf_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int qcom_osm_l3_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	icc_nodes_remove(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return icc_provider_del(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int qcom_osm_l3_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 info, src, lval, i, prev_freq = 0, freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	static unsigned long hw_rate, xo_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct qcom_osm_l3_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	const struct qcom_icc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct icc_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	const struct qcom_icc_node **qnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct icc_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	size_t num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	clk = clk_get(&pdev->dev, "xo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	xo_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	clk = clk_get(&pdev->dev, "alternate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	qp->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (IS_ERR(qp->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return PTR_ERR(qp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* HW should be in enabled state to proceed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		dev_err(&pdev->dev, "error hardware not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	desc = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	qp->reg_perf_state = desc->reg_perf_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		info = readl_relaxed(qp->base + desc->reg_freq_lut +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				     i * desc->lut_row_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		src = FIELD_GET(LUT_SRC, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		lval = FIELD_GET(LUT_L_VAL, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		if (src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			freq = xo_rate * lval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			freq = hw_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		/* Two of the same frequencies signify end of table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		if (i > 0 && prev_freq == freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		qp->lut_tables[i] = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		prev_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	qp->max_state = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	qnodes = desc->nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	num_nodes = desc->num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	provider = &qp->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	provider->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	provider->set = qcom_icc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	provider->aggregate = icc_std_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	provider->xlate = of_icc_xlate_onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	INIT_LIST_HEAD(&provider->nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	provider->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = icc_provider_add(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		dev_err(&pdev->dev, "error adding interconnect provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	for (i = 0; i < num_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		size_t j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		node = icc_node_create(qnodes[i]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		if (IS_ERR(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			ret = PTR_ERR(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		node->name = qnodes[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		/* Cast away const and add it back in qcom_icc_set() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		node->data = (void *)qnodes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		icc_node_add(node, provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		for (j = 0; j < qnodes[i]->num_links; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			icc_link_create(node, qnodes[i]->links[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		data->nodes[i] = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	data->num_nodes = num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	platform_set_drvdata(pdev, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	icc_nodes_remove(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	icc_provider_del(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct of_device_id osm_l3_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DEVICE_TABLE(of, osm_l3_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct platform_driver osm_l3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.probe = qcom_osm_l3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.remove = qcom_osm_l3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.name = "osm-l3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.of_match_table = osm_l3_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.sync_state = icc_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) module_platform_driver(osm_l3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MODULE_LICENSE("GPL v2");