^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 Brian Masney <masneyb@onstation.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on MSM bus code from downstream MSM kernel sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on qcs404.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2019 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Here's a rough representation that shows the various buses that form the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Network On Chip (NOC) for the msm8974:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Multimedia Subsystem (MMSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * |----------+-----------------------------------+-----------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Config | Bus Interface | Memory Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * |------------+-+-----------| |------------+-+-----------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * | System |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * |--------------+-+---------------------------------+-+-------------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Peripheral | On Chip | Memory (OCMEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * |------------+-------------| |------------+-------------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <dt-bindings/interconnect/qcom,msm8974.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "smd-rpm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MSM8974_BIMC_MAS_AMPSS_M0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MSM8974_BIMC_MAS_AMPSS_M1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MSM8974_BIMC_MAS_MSS_PROC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MSM8974_BIMC_TO_MNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MSM8974_BIMC_TO_SNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MSM8974_BIMC_SLV_EBI_CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MSM8974_BIMC_SLV_AMPSS_L2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MSM8974_CNOC_MAS_RPM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MSM8974_CNOC_MAS_RPM_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MSM8974_CNOC_MAS_RPM_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MSM8974_CNOC_MAS_DEHR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MSM8974_CNOC_MAS_QDSS_DAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MSM8974_CNOC_MAS_SPDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MSM8974_CNOC_MAS_TIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MSM8974_CNOC_SLV_CLK_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MSM8974_CNOC_SLV_CNOC_MSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MSM8974_CNOC_SLV_SECURITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MSM8974_CNOC_SLV_TCSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MSM8974_CNOC_SLV_TLMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MSM8974_CNOC_SLV_CRYPTO_0_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MSM8974_CNOC_SLV_CRYPTO_1_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MSM8974_CNOC_SLV_IMEM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MSM8974_CNOC_SLV_MESSAGE_RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MSM8974_CNOC_SLV_BIMC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MSM8974_CNOC_SLV_BOOT_ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MSM8974_CNOC_SLV_PMIC_ARB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MSM8974_CNOC_SLV_SPDM_WRAPPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MSM8974_CNOC_SLV_DEHR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MSM8974_CNOC_SLV_MPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MSM8974_CNOC_SLV_QDSS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MSM8974_CNOC_SLV_RBCPR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MSM8974_CNOC_TO_SNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MSM8974_CNOC_SLV_CNOC_ONOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MSM8974_CNOC_SLV_CNOC_MNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MSM8974_CNOC_SLV_PNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MSM8974_CNOC_SLV_SNOC_MPU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MSM8974_CNOC_SLV_SNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MSM8974_CNOC_SLV_EBI1_DLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MSM8974_CNOC_SLV_PHY_APU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MSM8974_CNOC_SLV_EBI1_PHY_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MSM8974_CNOC_SLV_RPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MSM8974_CNOC_SLV_SERVICE_CNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MSM8974_MNOC_MAS_GRAPHICS_3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MSM8974_MNOC_MAS_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MSM8974_MNOC_MAS_MDP_PORT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MSM8974_MNOC_MAS_VIDEO_P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MSM8974_MNOC_MAS_VIDEO_P1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MSM8974_MNOC_MAS_VFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MSM8974_MNOC_TO_CNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MSM8974_MNOC_TO_BIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MSM8974_MNOC_SLV_CAMERA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MSM8974_MNOC_SLV_DISPLAY_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MSM8974_MNOC_SLV_OCMEM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MSM8974_MNOC_SLV_CPR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MSM8974_MNOC_SLV_CPR_XPU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MSM8974_MNOC_SLV_MISC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MSM8974_MNOC_SLV_MISC_XPU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MSM8974_MNOC_SLV_VENUS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MSM8974_MNOC_SLV_GRAPHICS_3D_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MSM8974_MNOC_SLV_MMSS_CLK_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MSM8974_MNOC_SLV_MNOC_MPU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MSM8974_MNOC_SLV_ONOC_MPU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MSM8974_MNOC_SLV_SERVICE_MNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MSM8974_OCMEM_NOC_TO_OCMEM_VNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MSM8974_OCMEM_MAS_JPEG_OCMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MSM8974_OCMEM_MAS_MDP_OCMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MSM8974_OCMEM_MAS_VFE_OCMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MSM8974_OCMEM_MAS_CNOC_ONOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MSM8974_OCMEM_SLV_SERVICE_ONOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MSM8974_OCMEM_VNOC_TO_SNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MSM8974_OCMEM_VNOC_TO_OCMEM_NOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MSM8974_OCMEM_VNOC_MAS_GFX3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MSM8974_OCMEM_SLV_OCMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MSM8974_PNOC_MAS_PNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MSM8974_PNOC_MAS_SDCC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MSM8974_PNOC_MAS_SDCC_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MSM8974_PNOC_MAS_SDCC_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MSM8974_PNOC_MAS_SDCC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MSM8974_PNOC_MAS_TSIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MSM8974_PNOC_MAS_BAM_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MSM8974_PNOC_MAS_BLSP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MSM8974_PNOC_MAS_USB_HSIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MSM8974_PNOC_MAS_BLSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MSM8974_PNOC_MAS_USB_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MSM8974_PNOC_TO_SNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MSM8974_PNOC_SLV_SDCC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MSM8974_PNOC_SLV_SDCC_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MSM8974_PNOC_SLV_SDCC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MSM8974_PNOC_SLV_SDCC_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MSM8974_PNOC_SLV_TSIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MSM8974_PNOC_SLV_BAM_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MSM8974_PNOC_SLV_BLSP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MSM8974_PNOC_SLV_USB_HSIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MSM8974_PNOC_SLV_BLSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MSM8974_PNOC_SLV_USB_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MSM8974_PNOC_SLV_PDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MSM8974_PNOC_SLV_PERIPH_APU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MSM8974_PNOC_SLV_PNOC_MPU_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MSM8974_PNOC_SLV_PRNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MSM8974_PNOC_SLV_SERVICE_PNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MSM8974_SNOC_MAS_LPASS_AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MSM8974_SNOC_MAS_QDSS_BAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MSM8974_SNOC_MAS_SNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MSM8974_SNOC_TO_BIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MSM8974_SNOC_TO_CNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MSM8974_SNOC_TO_PNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MSM8974_SNOC_TO_OCMEM_VNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MSM8974_SNOC_MAS_CRYPTO_CORE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MSM8974_SNOC_MAS_CRYPTO_CORE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MSM8974_SNOC_MAS_LPASS_PROC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MSM8974_SNOC_MAS_MSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MSM8974_SNOC_MAS_MSS_NAV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MSM8974_SNOC_MAS_OCMEM_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MSM8974_SNOC_MAS_WCSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MSM8974_SNOC_MAS_QDSS_ETR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MSM8974_SNOC_MAS_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MSM8974_SNOC_SLV_AMPSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MSM8974_SNOC_SLV_LPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MSM8974_SNOC_SLV_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MSM8974_SNOC_SLV_WCSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MSM8974_SNOC_SLV_OCIMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MSM8974_SNOC_SLV_SNOC_OCMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MSM8974_SNOC_SLV_SERVICE_SNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MSM8974_SNOC_SLV_QDSS_STM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RPM_BUS_MASTER_REQ 0x73616d62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RPM_BUS_SLAVE_REQ 0x766c7362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define to_msm8974_icc_provider(_provider) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) container_of(_provider, struct msm8974_icc_provider, provider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct clk_bulk_data msm8974_icc_bus_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .id = "bus" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .id = "bus_a" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * struct msm8974_icc_provider - Qualcomm specific interconnect provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @provider: generic interconnect provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @bus_clks: the clk_bulk_data table of bus clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @num_clks: the total number of clk_bulk_data entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct msm8974_icc_provider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct icc_provider provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct clk_bulk_data *bus_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MSM8974_ICC_MAX_LINKS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * struct msm8974_icc_node - Qualcomm specific interconnect nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @name: the node name used in debugfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @id: a unique node identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @links: an array of nodes where we can go next while traversing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @num_links: the total number of @links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @buswidth: width of the interconnect between a node and the bus (bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @mas_rpm_id: RPM ID for devices that are bus masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @slv_rpm_id: RPM ID for devices that are bus slaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @rate: current bus clock rate in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct msm8974_icc_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 links[MSM8974_ICC_MAX_LINKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u16 num_links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u16 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int mas_rpm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int slv_rpm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct msm8974_icc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct msm8974_icc_node **nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) size_t num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct msm8974_icc_node _name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .buswidth = _buswidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .mas_rpm_id = _mas_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .slv_rpm_id = _slv_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .links = { __VA_ARGS__ }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) DEFINE_QNODE(mas_ampss_m0, MSM8974_BIMC_MAS_AMPSS_M0, 8, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DEFINE_QNODE(mas_ampss_m1, MSM8974_BIMC_MAS_AMPSS_M1, 8, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DEFINE_QNODE(mas_mss_proc, MSM8974_BIMC_MAS_MSS_PROC, 8, 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DEFINE_QNODE(bimc_to_mnoc, MSM8974_BIMC_TO_MNOC, 8, 2, -1, MSM8974_BIMC_SLV_EBI_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_BIMC, MSM8974_BIMC_SLV_EBI_CH0, MSM8974_BIMC_MAS_AMPSS_M0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct msm8974_icc_node *msm8974_bimc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [BIMC_MAS_AMPSS_M0] = &mas_ampss_m0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [BIMC_MAS_AMPSS_M1] = &mas_ampss_m1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [BIMC_MAS_MSS_PROC] = &mas_mss_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [BIMC_TO_MNOC] = &bimc_to_mnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [BIMC_TO_SNOC] = &bimc_to_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [BIMC_SLV_EBI_CH0] = &slv_ebi_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [BIMC_SLV_AMPSS_L2] = &slv_ampss_l2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct msm8974_icc_desc msm8974_bimc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .nodes = msm8974_bimc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .num_nodes = ARRAY_SIZE(msm8974_bimc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DEFINE_QNODE(mas_rpm_inst, MSM8974_CNOC_MAS_RPM_INST, 8, 45, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DEFINE_QNODE(mas_rpm_data, MSM8974_CNOC_MAS_RPM_DATA, 8, 46, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DEFINE_QNODE(mas_rpm_sys, MSM8974_CNOC_MAS_RPM_SYS, 8, 47, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DEFINE_QNODE(mas_dehr, MSM8974_CNOC_MAS_DEHR, 8, 48, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DEFINE_QNODE(mas_qdss_dap, MSM8974_CNOC_MAS_QDSS_DAP, 8, 49, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DEFINE_QNODE(mas_spdm, MSM8974_CNOC_MAS_SPDM, 8, 50, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DEFINE_QNODE(mas_tic, MSM8974_CNOC_MAS_TIC, 8, 51, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DEFINE_QNODE(slv_clk_ctl, MSM8974_CNOC_SLV_CLK_CTL, 8, -1, 47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DEFINE_QNODE(slv_cnoc_mss, MSM8974_CNOC_SLV_CNOC_MSS, 8, -1, 48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DEFINE_QNODE(slv_security, MSM8974_CNOC_SLV_SECURITY, 8, -1, 49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DEFINE_QNODE(slv_tcsr, MSM8974_CNOC_SLV_TCSR, 8, -1, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DEFINE_QNODE(slv_tlmm, MSM8974_CNOC_SLV_TLMM, 8, -1, 51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DEFINE_QNODE(slv_crypto_0_cfg, MSM8974_CNOC_SLV_CRYPTO_0_CFG, 8, -1, 52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DEFINE_QNODE(slv_crypto_1_cfg, MSM8974_CNOC_SLV_CRYPTO_1_CFG, 8, -1, 53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DEFINE_QNODE(slv_imem_cfg, MSM8974_CNOC_SLV_IMEM_CFG, 8, -1, 54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DEFINE_QNODE(slv_message_ram, MSM8974_CNOC_SLV_MESSAGE_RAM, 8, -1, 55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DEFINE_QNODE(slv_bimc_cfg, MSM8974_CNOC_SLV_BIMC_CFG, 8, -1, 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DEFINE_QNODE(slv_boot_rom, MSM8974_CNOC_SLV_BOOT_ROM, 8, -1, 57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DEFINE_QNODE(slv_pmic_arb, MSM8974_CNOC_SLV_PMIC_ARB, 8, -1, 59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DEFINE_QNODE(slv_spdm_wrapper, MSM8974_CNOC_SLV_SPDM_WRAPPER, 8, -1, 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DEFINE_QNODE(slv_dehr_cfg, MSM8974_CNOC_SLV_DEHR_CFG, 8, -1, 61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DEFINE_QNODE(slv_mpm, MSM8974_CNOC_SLV_MPM, 8, -1, 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DEFINE_QNODE(slv_qdss_cfg, MSM8974_CNOC_SLV_QDSS_CFG, 8, -1, 63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DEFINE_QNODE(slv_rbcpr_cfg, MSM8974_CNOC_SLV_RBCPR_CFG, 8, -1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DEFINE_QNODE(slv_rbcpr_qdss_apu_cfg, MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, 8, -1, 65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DEFINE_QNODE(cnoc_to_snoc, MSM8974_CNOC_TO_SNOC, 8, 52, 75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DEFINE_QNODE(slv_cnoc_onoc_cfg, MSM8974_CNOC_SLV_CNOC_ONOC_CFG, 8, -1, 68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, 8, -1, 58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_CFG, 8, -1, 66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DEFINE_QNODE(slv_pnoc_cfg, MSM8974_CNOC_SLV_PNOC_CFG, 8, -1, 69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DEFINE_QNODE(slv_snoc_mpu_cfg, MSM8974_CNOC_SLV_SNOC_MPU_CFG, 8, -1, 67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DEFINE_QNODE(slv_snoc_cfg, MSM8974_CNOC_SLV_SNOC_CFG, 8, -1, 70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DEFINE_QNODE(slv_ebi1_dll_cfg, MSM8974_CNOC_SLV_EBI1_DLL_CFG, 8, -1, 71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DEFINE_QNODE(slv_phy_apu_cfg, MSM8974_CNOC_SLV_PHY_APU_CFG, 8, -1, 72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct msm8974_icc_node *msm8974_cnoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [CNOC_MAS_RPM_INST] = &mas_rpm_inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [CNOC_MAS_RPM_DATA] = &mas_rpm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [CNOC_MAS_RPM_SYS] = &mas_rpm_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [CNOC_MAS_DEHR] = &mas_dehr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [CNOC_MAS_QDSS_DAP] = &mas_qdss_dap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [CNOC_MAS_SPDM] = &mas_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [CNOC_MAS_TIC] = &mas_tic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [CNOC_SLV_CLK_CTL] = &slv_clk_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [CNOC_SLV_CNOC_MSS] = &slv_cnoc_mss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [CNOC_SLV_SECURITY] = &slv_security,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [CNOC_SLV_TCSR] = &slv_tcsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [CNOC_SLV_TLMM] = &slv_tlmm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [CNOC_SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [CNOC_SLV_CRYPTO_1_CFG] = &slv_crypto_1_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [CNOC_SLV_IMEM_CFG] = &slv_imem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [CNOC_SLV_MESSAGE_RAM] = &slv_message_ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [CNOC_SLV_BIMC_CFG] = &slv_bimc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [CNOC_SLV_BOOT_ROM] = &slv_boot_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [CNOC_SLV_PMIC_ARB] = &slv_pmic_arb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [CNOC_SLV_SPDM_WRAPPER] = &slv_spdm_wrapper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [CNOC_SLV_DEHR_CFG] = &slv_dehr_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [CNOC_SLV_MPM] = &slv_mpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [CNOC_SLV_QDSS_CFG] = &slv_qdss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [CNOC_SLV_RBCPR_CFG] = &slv_rbcpr_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [CNOC_SLV_RBCPR_QDSS_APU_CFG] = &slv_rbcpr_qdss_apu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [CNOC_TO_SNOC] = &cnoc_to_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [CNOC_SLV_CNOC_ONOC_CFG] = &slv_cnoc_onoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [CNOC_SLV_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [CNOC_SLV_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [CNOC_SLV_PNOC_CFG] = &slv_pnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [CNOC_SLV_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [CNOC_SLV_SNOC_CFG] = &slv_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [CNOC_SLV_EBI1_DLL_CFG] = &slv_ebi1_dll_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [CNOC_SLV_PHY_APU_CFG] = &slv_phy_apu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [CNOC_SLV_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [CNOC_SLV_RPM] = &slv_rpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct msm8974_icc_desc msm8974_cnoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .nodes = msm8974_cnoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DEFINE_QNODE(mas_graphics_3d, MSM8974_MNOC_MAS_GRAPHICS_3D, 16, 6, -1, MSM8974_MNOC_TO_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DEFINE_QNODE(mas_jpeg, MSM8974_MNOC_MAS_JPEG, 16, 7, -1, MSM8974_MNOC_TO_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DEFINE_QNODE(mas_mdp_port0, MSM8974_MNOC_MAS_MDP_PORT0, 16, 8, -1, MSM8974_MNOC_TO_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DEFINE_QNODE(mas_video_p0, MSM8974_MNOC_MAS_VIDEO_P0, 16, 9, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DEFINE_QNODE(mas_video_p1, MSM8974_MNOC_MAS_VIDEO_P1, 16, 10, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DEFINE_QNODE(mas_vfe, MSM8974_MNOC_MAS_VFE, 16, 11, -1, MSM8974_MNOC_TO_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DEFINE_QNODE(mnoc_to_cnoc, MSM8974_MNOC_TO_CNOC, 16, 4, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DEFINE_QNODE(mnoc_to_bimc, MSM8974_MNOC_TO_BIMC, 16, -1, 16, MSM8974_BIMC_TO_MNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DEFINE_QNODE(slv_camera_cfg, MSM8974_MNOC_SLV_CAMERA_CFG, 16, -1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DEFINE_QNODE(slv_display_cfg, MSM8974_MNOC_SLV_DISPLAY_CFG, 16, -1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DEFINE_QNODE(slv_ocmem_cfg, MSM8974_MNOC_SLV_OCMEM_CFG, 16, -1, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DEFINE_QNODE(slv_cpr_cfg, MSM8974_MNOC_SLV_CPR_CFG, 16, -1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DEFINE_QNODE(slv_cpr_xpu_cfg, MSM8974_MNOC_SLV_CPR_XPU_CFG, 16, -1, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DEFINE_QNODE(slv_misc_cfg, MSM8974_MNOC_SLV_MISC_CFG, 16, -1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DEFINE_QNODE(slv_misc_xpu_cfg, MSM8974_MNOC_SLV_MISC_XPU_CFG, 16, -1, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DEFINE_QNODE(slv_venus_cfg, MSM8974_MNOC_SLV_VENUS_CFG, 16, -1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DEFINE_QNODE(slv_graphics_3d_cfg, MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, 16, -1, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DEFINE_QNODE(slv_mmss_clk_cfg, MSM8974_MNOC_SLV_MMSS_CLK_CFG, 16, -1, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DEFINE_QNODE(slv_mmss_clk_xpu_cfg, MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, 16, -1, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct msm8974_icc_node *msm8974_mnoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) [MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [MNOC_MAS_JPEG] = &mas_jpeg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [MNOC_MAS_MDP_PORT0] = &mas_mdp_port0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [MNOC_MAS_VIDEO_P0] = &mas_video_p0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [MNOC_MAS_VIDEO_P1] = &mas_video_p1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [MNOC_MAS_VFE] = &mas_vfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [MNOC_TO_CNOC] = &mnoc_to_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [MNOC_TO_BIMC] = &mnoc_to_bimc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [MNOC_SLV_CAMERA_CFG] = &slv_camera_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [MNOC_SLV_DISPLAY_CFG] = &slv_display_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [MNOC_SLV_OCMEM_CFG] = &slv_ocmem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [MNOC_SLV_CPR_CFG] = &slv_cpr_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [MNOC_SLV_CPR_XPU_CFG] = &slv_cpr_xpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [MNOC_SLV_MISC_CFG] = &slv_misc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [MNOC_SLV_MISC_XPU_CFG] = &slv_misc_xpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) [MNOC_SLV_VENUS_CFG] = &slv_venus_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) [MNOC_SLV_GRAPHICS_3D_CFG] = &slv_graphics_3d_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [MNOC_SLV_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [MNOC_SLV_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) [MNOC_SLV_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [MNOC_SLV_ONOC_MPU_CFG] = &slv_onoc_mpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct msm8974_icc_desc msm8974_mnoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .nodes = msm8974_mnoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DEFINE_QNODE(ocmem_noc_to_ocmem_vnoc, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 16, 54, 78, MSM8974_OCMEM_SLV_OCMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DEFINE_QNODE(mas_jpeg_ocmem, MSM8974_OCMEM_MAS_JPEG_OCMEM, 16, 13, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DEFINE_QNODE(mas_mdp_ocmem, MSM8974_OCMEM_MAS_MDP_OCMEM, 16, 14, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DEFINE_QNODE(mas_video_p0_ocmem, MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, 16, 15, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DEFINE_QNODE(mas_video_p1_ocmem, MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, 16, 16, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DEFINE_QNODE(mas_vfe_ocmem, MSM8974_OCMEM_MAS_VFE_OCMEM, 16, 17, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DEFINE_QNODE(mas_cnoc_onoc_cfg, MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, 16, 12, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DEFINE_QNODE(slv_service_onoc, MSM8974_OCMEM_SLV_SERVICE_ONOC, 16, -1, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DEFINE_QNODE(slv_ocmem, MSM8974_OCMEM_SLV_OCMEM, 16, -1, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Virtual NoC is needed for connection to OCMEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, 79, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static struct msm8974_icc_node *msm8974_onoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [OCMEM_MAS_VIDEO_P0_OCMEM] = &mas_video_p0_ocmem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) [OCMEM_MAS_VIDEO_P1_OCMEM] = &mas_video_p1_ocmem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [OCMEM_MAS_VFE_OCMEM] = &mas_vfe_ocmem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) [OCMEM_MAS_CNOC_ONOC_CFG] = &mas_cnoc_onoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [OCMEM_SLV_SERVICE_ONOC] = &slv_service_onoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [OCMEM_VNOC_TO_SNOC] = &ocmem_vnoc_to_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [OCMEM_VNOC_TO_OCMEM_NOC] = &ocmem_vnoc_to_onoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [OCMEM_VNOC_MAS_GFX3D] = &mas_v_ocmem_gfx3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [OCMEM_SLV_OCMEM] = &slv_ocmem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct msm8974_icc_desc msm8974_onoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .nodes = msm8974_onoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .num_nodes = ARRAY_SIZE(msm8974_onoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DEFINE_QNODE(mas_pnoc_cfg, MSM8974_PNOC_MAS_PNOC_CFG, 8, 43, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DEFINE_QNODE(mas_sdcc_1, MSM8974_PNOC_MAS_SDCC_1, 8, 33, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DEFINE_QNODE(mas_sdcc_3, MSM8974_PNOC_MAS_SDCC_3, 8, 34, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DEFINE_QNODE(mas_sdcc_4, MSM8974_PNOC_MAS_SDCC_4, 8, 36, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DEFINE_QNODE(mas_sdcc_2, MSM8974_PNOC_MAS_SDCC_2, 8, 35, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DEFINE_QNODE(mas_tsif, MSM8974_PNOC_MAS_TSIF, 8, 37, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DEFINE_QNODE(mas_bam_dma, MSM8974_PNOC_MAS_BAM_DMA, 8, 38, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DEFINE_QNODE(mas_blsp_2, MSM8974_PNOC_MAS_BLSP_2, 8, 39, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DEFINE_QNODE(mas_usb_hsic, MSM8974_PNOC_MAS_USB_HSIC, 8, 40, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DEFINE_QNODE(mas_blsp_1, MSM8974_PNOC_MAS_BLSP_1, 8, 41, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DEFINE_QNODE(mas_usb_hs, MSM8974_PNOC_MAS_USB_HS, 8, 42, -1, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DEFINE_QNODE(pnoc_to_snoc, MSM8974_PNOC_TO_SNOC, 8, 44, 45, MSM8974_SNOC_TO_PNOC, MSM8974_PNOC_SLV_PRNG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) DEFINE_QNODE(slv_sdcc_1, MSM8974_PNOC_SLV_SDCC_1, 8, -1, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DEFINE_QNODE(slv_sdcc_3, MSM8974_PNOC_SLV_SDCC_3, 8, -1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DEFINE_QNODE(slv_sdcc_2, MSM8974_PNOC_SLV_SDCC_2, 8, -1, 33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DEFINE_QNODE(slv_sdcc_4, MSM8974_PNOC_SLV_SDCC_4, 8, -1, 34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) DEFINE_QNODE(slv_tsif, MSM8974_PNOC_SLV_TSIF, 8, -1, 35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DEFINE_QNODE(slv_bam_dma, MSM8974_PNOC_SLV_BAM_DMA, 8, -1, 36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) DEFINE_QNODE(slv_blsp_2, MSM8974_PNOC_SLV_BLSP_2, 8, -1, 37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) DEFINE_QNODE(slv_usb_hsic, MSM8974_PNOC_SLV_USB_HSIC, 8, -1, 38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) DEFINE_QNODE(slv_blsp_1, MSM8974_PNOC_SLV_BLSP_1, 8, -1, 39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) DEFINE_QNODE(slv_usb_hs, MSM8974_PNOC_SLV_USB_HS, 8, -1, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) DEFINE_QNODE(slv_pdm, MSM8974_PNOC_SLV_PDM, 8, -1, 41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DEFINE_QNODE(slv_periph_apu_cfg, MSM8974_PNOC_SLV_PERIPH_APU_CFG, 8, -1, 42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct msm8974_icc_node *msm8974_pnoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) [PNOC_MAS_SDCC_1] = &mas_sdcc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) [PNOC_MAS_SDCC_3] = &mas_sdcc_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [PNOC_MAS_SDCC_4] = &mas_sdcc_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [PNOC_MAS_SDCC_2] = &mas_sdcc_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [PNOC_MAS_TSIF] = &mas_tsif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [PNOC_MAS_BAM_DMA] = &mas_bam_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [PNOC_MAS_BLSP_2] = &mas_blsp_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [PNOC_MAS_USB_HSIC] = &mas_usb_hsic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [PNOC_MAS_BLSP_1] = &mas_blsp_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) [PNOC_MAS_USB_HS] = &mas_usb_hs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [PNOC_TO_SNOC] = &pnoc_to_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [PNOC_SLV_SDCC_1] = &slv_sdcc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [PNOC_SLV_SDCC_3] = &slv_sdcc_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) [PNOC_SLV_SDCC_2] = &slv_sdcc_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) [PNOC_SLV_SDCC_4] = &slv_sdcc_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) [PNOC_SLV_TSIF] = &slv_tsif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [PNOC_SLV_BAM_DMA] = &slv_bam_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [PNOC_SLV_BLSP_2] = &slv_blsp_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [PNOC_SLV_USB_HSIC] = &slv_usb_hsic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [PNOC_SLV_BLSP_1] = &slv_blsp_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [PNOC_SLV_USB_HS] = &slv_usb_hs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [PNOC_SLV_PDM] = &slv_pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [PNOC_SLV_PERIPH_APU_CFG] = &slv_periph_apu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [PNOC_SLV_PNOC_MPU_CFG] = &slv_pnoc_mpu_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [PNOC_SLV_PRNG] = &slv_prng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct msm8974_icc_desc msm8974_pnoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .nodes = msm8974_pnoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DEFINE_QNODE(mas_lpass_ahb, MSM8974_SNOC_MAS_LPASS_AHB, 8, 18, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) DEFINE_QNODE(mas_qdss_bam, MSM8974_SNOC_MAS_QDSS_BAM, 8, 19, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) DEFINE_QNODE(mas_snoc_cfg, MSM8974_SNOC_MAS_SNOC_CFG, 8, 20, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DEFINE_QNODE(snoc_to_bimc, MSM8974_SNOC_TO_BIMC, 8, 21, 24, MSM8974_BIMC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) DEFINE_QNODE(snoc_to_cnoc, MSM8974_SNOC_TO_CNOC, 8, 22, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) DEFINE_QNODE(snoc_to_pnoc, MSM8974_SNOC_TO_PNOC, 8, 29, 28, MSM8974_PNOC_TO_SNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DEFINE_QNODE(snoc_to_ocmem_vnoc, MSM8974_SNOC_TO_OCMEM_VNOC, 8, 53, 77, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DEFINE_QNODE(mas_crypto_core0, MSM8974_SNOC_MAS_CRYPTO_CORE0, 8, 23, -1, MSM8974_SNOC_TO_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DEFINE_QNODE(mas_crypto_core1, MSM8974_SNOC_MAS_CRYPTO_CORE1, 8, 24, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DEFINE_QNODE(mas_lpass_proc, MSM8974_SNOC_MAS_LPASS_PROC, 8, 25, -1, MSM8974_SNOC_TO_OCMEM_VNOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DEFINE_QNODE(mas_mss, MSM8974_SNOC_MAS_MSS, 8, 26, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DEFINE_QNODE(mas_mss_nav, MSM8974_SNOC_MAS_MSS_NAV, 8, 27, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DEFINE_QNODE(mas_ocmem_dma, MSM8974_SNOC_MAS_OCMEM_DMA, 8, 28, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DEFINE_QNODE(mas_wcss, MSM8974_SNOC_MAS_WCSS, 8, 30, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DEFINE_QNODE(mas_qdss_etr, MSM8974_SNOC_MAS_QDSS_ETR, 8, 31, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DEFINE_QNODE(mas_usb3, MSM8974_SNOC_MAS_USB3, 8, 32, -1, MSM8974_SNOC_TO_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DEFINE_QNODE(slv_ampss, MSM8974_SNOC_SLV_AMPSS, 8, -1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DEFINE_QNODE(slv_lpass, MSM8974_SNOC_SLV_LPASS, 8, -1, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DEFINE_QNODE(slv_usb3, MSM8974_SNOC_SLV_USB3, 8, -1, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DEFINE_QNODE(slv_wcss, MSM8974_SNOC_SLV_WCSS, 8, -1, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DEFINE_QNODE(slv_ocimem, MSM8974_SNOC_SLV_OCIMEM, 8, -1, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static struct msm8974_icc_node *msm8974_snoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) [SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [SNOC_MAS_QDSS_BAM] = &mas_qdss_bam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) [SNOC_TO_BIMC] = &snoc_to_bimc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) [SNOC_TO_CNOC] = &snoc_to_cnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [SNOC_TO_PNOC] = &snoc_to_pnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [SNOC_TO_OCMEM_VNOC] = &snoc_to_ocmem_vnoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [SNOC_MAS_CRYPTO_CORE0] = &mas_crypto_core0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [SNOC_MAS_CRYPTO_CORE1] = &mas_crypto_core1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [SNOC_MAS_LPASS_PROC] = &mas_lpass_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [SNOC_MAS_MSS] = &mas_mss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [SNOC_MAS_MSS_NAV] = &mas_mss_nav,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [SNOC_MAS_OCMEM_DMA] = &mas_ocmem_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [SNOC_MAS_WCSS] = &mas_wcss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [SNOC_MAS_QDSS_ETR] = &mas_qdss_etr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) [SNOC_MAS_USB3] = &mas_usb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [SNOC_SLV_AMPSS] = &slv_ampss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [SNOC_SLV_LPASS] = &slv_lpass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) [SNOC_SLV_USB3] = &slv_usb3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) [SNOC_SLV_WCSS] = &slv_wcss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) [SNOC_SLV_OCIMEM] = &slv_ocimem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [SNOC_SLV_SNOC_OCMEM] = &slv_snoc_ocmem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) [SNOC_SLV_SERVICE_SNOC] = &slv_service_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) [SNOC_SLV_QDSS_STM] = &slv_qdss_stm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static struct msm8974_icc_desc msm8974_snoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .nodes = msm8974_snoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .num_nodes = ARRAY_SIZE(msm8974_snoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void msm8974_icc_rpm_smd_send(struct device *dev, int rsc_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) char *name, int id, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (id == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Setting the bandwidth requests for some nodes fails and this same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * behavior occurs on the downstream MSM 3.4 kernel sources based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * errors like this in that kernel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * msm_rpm_get_error_from_ack(): RPM NACK Unsupported resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * AXI: msm_bus_rpm_req(): RPM: Ack failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * AXI: msm_bus_rpm_commit_arb(): RPM: Req fail: mas:32, bw:240000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * Since there's no publicly available documentation for this hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * and the bandwidth for some nodes in the path can be set properly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * let's not return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, rsc_type, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_dbg(dev, "Cannot set bandwidth for node %s (%d): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) name, id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct msm8974_icc_node *src_qn, *dst_qn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct msm8974_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u64 sum_bw, max_peak_bw, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 agg_avg = 0, agg_peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct icc_node *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) src_qn = src->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dst_qn = dst->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) provider = src->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) qp = to_msm8974_icc_provider(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) list_for_each_entry(n, &provider->nodes, node_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &agg_avg, &agg_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) sum_bw = icc_units_to_bps(agg_avg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) max_peak_bw = icc_units_to_bps(agg_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Set bandwidth on source node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) src_qn->name, src_qn->mas_rpm_id, sum_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) src_qn->name, src_qn->slv_rpm_id, sum_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Set bandwidth on destination node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dst_qn->name, dst_qn->mas_rpm_id, sum_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dst_qn->name, dst_qn->slv_rpm_id, sum_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) rate = max(sum_bw, max_peak_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) do_div(rate, src_qn->buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) rate = min_t(u32, rate, INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (src_qn->rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) for (i = 0; i < qp->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = clk_set_rate(qp->bus_clks[i].clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_err(provider->dev, "%s clk_set_rate error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) qp->bus_clks[i].id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) src_qn->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *avg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int msm8974_icc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) const struct msm8974_icc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct msm8974_icc_node **qnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct msm8974_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct icc_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct icc_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) size_t num_nodes, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* wait for the RPM proxy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!qcom_icc_rpm_smd_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) desc = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) qnodes = desc->nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) num_nodes = desc->num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) qp->bus_clks = devm_kmemdup(dev, msm8974_icc_bus_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) sizeof(msm8974_icc_bus_clocks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!qp->bus_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) qp->num_clks = ARRAY_SIZE(msm8974_icc_bus_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) provider = &qp->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) INIT_LIST_HEAD(&provider->nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) provider->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) provider->set = msm8974_icc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) provider->aggregate = icc_std_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) provider->xlate = of_icc_xlate_onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) provider->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) provider->get_bw = msm8974_get_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = icc_provider_add(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_err(dev, "error adding interconnect provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto err_disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) for (i = 0; i < num_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) size_t j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) node = icc_node_create(qnodes[i]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (IS_ERR(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = PTR_ERR(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) goto err_del_icc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) node->name = qnodes[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) node->data = qnodes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) icc_node_add(node, provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_dbg(dev, "registered node %s\n", node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* populate links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) for (j = 0; j < qnodes[i]->num_links; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) icc_link_create(node, qnodes[i]->links[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) data->nodes[i] = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) data->num_nodes = num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) platform_set_drvdata(pdev, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) err_del_icc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) icc_nodes_remove(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) icc_provider_del(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err_disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int msm8974_icc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct msm8974_icc_provider *qp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) icc_nodes_remove(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return icc_provider_del(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const struct of_device_id msm8974_noc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) { .compatible = "qcom,msm8974-bimc", .data = &msm8974_bimc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { .compatible = "qcom,msm8974-cnoc", .data = &msm8974_cnoc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { .compatible = "qcom,msm8974-mmssnoc", .data = &msm8974_mnoc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { .compatible = "qcom,msm8974-ocmemnoc", .data = &msm8974_onoc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { .compatible = "qcom,msm8974-pnoc", .data = &msm8974_pnoc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) { .compatible = "qcom,msm8974-snoc", .data = &msm8974_snoc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) MODULE_DEVICE_TABLE(of, msm8974_noc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static struct platform_driver msm8974_noc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .probe = msm8974_icc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .remove = msm8974_icc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .name = "qnoc-msm8974",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .of_match_table = msm8974_noc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .sync_state = icc_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) module_platform_driver(msm8974_noc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) MODULE_DESCRIPTION("Qualcomm MSM8974 NoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) MODULE_AUTHOR("Brian Masney <masneyb@onstation.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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