^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018-2020 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Georgi Djakov <georgi.djakov@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/interconnect/qcom,msm8916.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "smd-rpm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RPM_BUS_MASTER_REQ 0x73616d62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RPM_BUS_SLAVE_REQ 0x766c7362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MSM8916_BIMC_SNOC_MAS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MSM8916_BIMC_SNOC_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MSM8916_MASTER_AMPSS_M0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MSM8916_MASTER_LPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MSM8916_MASTER_BLSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MSM8916_MASTER_DEHR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MSM8916_MASTER_GRAPHICS_3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MSM8916_MASTER_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MSM8916_MASTER_MDP_PORT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MSM8916_MASTER_CRYPTO_CORE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MSM8916_MASTER_SDCC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MSM8916_MASTER_SDCC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MSM8916_MASTER_QDSS_BAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MSM8916_MASTER_QDSS_ETR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MSM8916_MASTER_SNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MSM8916_MASTER_SPDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MSM8916_MASTER_TCU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MSM8916_MASTER_TCU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MSM8916_MASTER_USB_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MSM8916_MASTER_VFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MSM8916_MASTER_VIDEO_P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MSM8916_SNOC_MM_INT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MSM8916_SNOC_MM_INT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MSM8916_SNOC_MM_INT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MSM8916_SNOC_MM_INT_BIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MSM8916_PNOC_INT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MSM8916_PNOC_INT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MSM8916_PNOC_MAS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MSM8916_PNOC_MAS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MSM8916_PNOC_SLV_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MSM8916_PNOC_SLV_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MSM8916_PNOC_SLV_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MSM8916_PNOC_SLV_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MSM8916_PNOC_SLV_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MSM8916_PNOC_SLV_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MSM8916_PNOC_SLV_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MSM8916_PNOC_SNOC_MAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MSM8916_PNOC_SNOC_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MSM8916_SNOC_QDSS_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MSM8916_SLAVE_AMPSS_L2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MSM8916_SLAVE_APSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MSM8916_SLAVE_LPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MSM8916_SLAVE_BIMC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MSM8916_SLAVE_BLSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MSM8916_SLAVE_BOOT_ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MSM8916_SLAVE_CAMERA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MSM8916_SLAVE_CATS_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MSM8916_SLAVE_OCMEM_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MSM8916_SLAVE_CLK_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MSM8916_SLAVE_CRYPTO_0_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MSM8916_SLAVE_DEHR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MSM8916_SLAVE_DISPLAY_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MSM8916_SLAVE_EBI_CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MSM8916_SLAVE_GRAPHICS_3D_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MSM8916_SLAVE_IMEM_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MSM8916_SLAVE_IMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MSM8916_SLAVE_MPM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MSM8916_SLAVE_MSG_RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MSM8916_SLAVE_MSS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MSM8916_SLAVE_PDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MSM8916_SLAVE_PMIC_ARB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MSM8916_SLAVE_PNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MSM8916_SLAVE_PRNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MSM8916_SLAVE_QDSS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MSM8916_SLAVE_QDSS_STM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MSM8916_SLAVE_RBCPR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MSM8916_SLAVE_SDCC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MSM8916_SLAVE_SDCC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MSM8916_SLAVE_SECURITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MSM8916_SLAVE_SNOC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MSM8916_SLAVE_SPDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MSM8916_SLAVE_SRVC_SNOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MSM8916_SLAVE_TCSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MSM8916_SLAVE_TLMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MSM8916_SLAVE_USB_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MSM8916_SLAVE_VENUS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MSM8916_SNOC_BIMC_0_MAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MSM8916_SNOC_BIMC_0_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MSM8916_SNOC_BIMC_1_MAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MSM8916_SNOC_BIMC_1_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MSM8916_SNOC_INT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MSM8916_SNOC_INT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MSM8916_SNOC_INT_BIMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MSM8916_SNOC_PNOC_MAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MSM8916_SNOC_PNOC_SLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define to_msm8916_provider(_provider) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) container_of(_provider, struct msm8916_icc_provider, provider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct clk_bulk_data msm8916_bus_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { .id = "bus" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { .id = "bus_a" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * struct msm8916_icc_provider - Qualcomm specific interconnect provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @provider: generic interconnect provider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @bus_clks: the clk_bulk_data table of bus clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @num_clks: the total number of clk_bulk_data entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct msm8916_icc_provider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct icc_provider provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk_bulk_data *bus_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MSM8916_MAX_LINKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * struct msm8916_icc_node - Qualcomm specific interconnect nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @name: the node name used in debugfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @id: a unique node identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @links: an array of nodes where we can go next while traversing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @num_links: the total number of @links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @buswidth: width of the interconnect between a node and the bus (bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @mas_rpm_id: RPM ID for devices that are bus masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @slv_rpm_id: RPM ID for devices that are bus slaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @rate: current bus clock rate in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct msm8916_icc_node {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 links[MSM8916_MAX_LINKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u16 num_links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int mas_rpm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int slv_rpm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct msm8916_icc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct msm8916_icc_node **nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) size_t num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct msm8916_icc_node _name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .buswidth = _buswidth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .mas_rpm_id = _mas_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .slv_rpm_id = _slv_rpm_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .links = { __VA_ARGS__ }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DEFINE_QNODE(bimc_snoc_mas, MSM8916_BIMC_SNOC_MAS, 8, -1, -1, MSM8916_BIMC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEFINE_QNODE(bimc_snoc_slv, MSM8916_BIMC_SNOC_SLV, 8, -1, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEFINE_QNODE(mas_apss, MSM8916_MASTER_AMPSS_M0, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DEFINE_QNODE(mas_audio, MSM8916_MASTER_LPASS, 4, -1, -1, MSM8916_PNOC_MAS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DEFINE_QNODE(mas_blsp_1, MSM8916_MASTER_BLSP_1, 4, -1, -1, MSM8916_PNOC_MAS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DEFINE_QNODE(mas_dehr, MSM8916_MASTER_DEHR, 4, -1, -1, MSM8916_PNOC_MAS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEFINE_QNODE(mas_gfx, MSM8916_MASTER_GRAPHICS_3D, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEFINE_QNODE(mas_jpeg, MSM8916_MASTER_JPEG, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEFINE_QNODE(mas_mdp, MSM8916_MASTER_MDP_PORT0, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEFINE_QNODE(mas_pcnoc_crypto_0, MSM8916_MASTER_CRYPTO_CORE0, 8, -1, -1, MSM8916_PNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEFINE_QNODE(mas_pcnoc_sdcc_1, MSM8916_MASTER_SDCC_1, 8, -1, -1, MSM8916_PNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DEFINE_QNODE(mas_pcnoc_sdcc_2, MSM8916_MASTER_SDCC_2, 8, -1, -1, MSM8916_PNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEFINE_QNODE(mas_qdss_bam, MSM8916_MASTER_QDSS_BAM, 8, -1, -1, MSM8916_SNOC_QDSS_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEFINE_QNODE(mas_qdss_etr, MSM8916_MASTER_QDSS_ETR, 8, -1, -1, MSM8916_SNOC_QDSS_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEFINE_QNODE(mas_snoc_cfg, MSM8916_MASTER_SNOC_CFG, 4, -1, -1, MSM8916_SNOC_QDSS_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DEFINE_QNODE(mas_spdm, MSM8916_MASTER_SPDM, 4, -1, -1, MSM8916_PNOC_MAS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DEFINE_QNODE(mas_tcu0, MSM8916_MASTER_TCU0, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DEFINE_QNODE(mas_tcu1, MSM8916_MASTER_TCU1, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DEFINE_QNODE(mas_usb_hs, MSM8916_MASTER_USB_HS, 4, -1, -1, MSM8916_PNOC_MAS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DEFINE_QNODE(mas_vfe, MSM8916_MASTER_VFE, 16, -1, -1, MSM8916_SNOC_MM_INT_1, MSM8916_SNOC_MM_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DEFINE_QNODE(mas_video, MSM8916_MASTER_VIDEO_P0, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DEFINE_QNODE(mm_int_0, MSM8916_SNOC_MM_INT_0, 16, -1, -1, MSM8916_SNOC_MM_INT_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DEFINE_QNODE(mm_int_1, MSM8916_SNOC_MM_INT_1, 16, -1, -1, MSM8916_SNOC_MM_INT_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DEFINE_QNODE(mm_int_2, MSM8916_SNOC_MM_INT_2, 16, -1, -1, MSM8916_SNOC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DEFINE_QNODE(mm_int_bimc, MSM8916_SNOC_MM_INT_BIMC, 16, -1, -1, MSM8916_SNOC_BIMC_1_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DEFINE_QNODE(pcnoc_int_0, MSM8916_PNOC_INT_0, 8, -1, -1, MSM8916_PNOC_SNOC_MAS, MSM8916_PNOC_SLV_0, MSM8916_PNOC_SLV_1, MSM8916_PNOC_SLV_2, MSM8916_PNOC_SLV_3, MSM8916_PNOC_SLV_4, MSM8916_PNOC_SLV_8, MSM8916_PNOC_SLV_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DEFINE_QNODE(pcnoc_int_1, MSM8916_PNOC_INT_1, 8, -1, -1, MSM8916_PNOC_SNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DEFINE_QNODE(pcnoc_m_0, MSM8916_PNOC_MAS_0, 8, -1, -1, MSM8916_PNOC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DEFINE_QNODE(pcnoc_m_1, MSM8916_PNOC_MAS_1, 8, -1, -1, MSM8916_PNOC_SNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DEFINE_QNODE(pcnoc_s_0, MSM8916_PNOC_SLV_0, 4, -1, -1, MSM8916_SLAVE_CLK_CTL, MSM8916_SLAVE_TLMM, MSM8916_SLAVE_TCSR, MSM8916_SLAVE_SECURITY, MSM8916_SLAVE_MSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DEFINE_QNODE(pcnoc_s_1, MSM8916_PNOC_SLV_1, 4, -1, -1, MSM8916_SLAVE_IMEM_CFG, MSM8916_SLAVE_CRYPTO_0_CFG, MSM8916_SLAVE_MSG_RAM, MSM8916_SLAVE_PDM, MSM8916_SLAVE_PRNG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DEFINE_QNODE(pcnoc_s_2, MSM8916_PNOC_SLV_2, 4, -1, -1, MSM8916_SLAVE_SPDM, MSM8916_SLAVE_BOOT_ROM, MSM8916_SLAVE_BIMC_CFG, MSM8916_SLAVE_PNOC_CFG, MSM8916_SLAVE_PMIC_ARB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DEFINE_QNODE(pcnoc_s_3, MSM8916_PNOC_SLV_3, 4, -1, -1, MSM8916_SLAVE_MPM, MSM8916_SLAVE_SNOC_CFG, MSM8916_SLAVE_RBCPR_CFG, MSM8916_SLAVE_QDSS_CFG, MSM8916_SLAVE_DEHR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DEFINE_QNODE(pcnoc_s_4, MSM8916_PNOC_SLV_4, 4, -1, -1, MSM8916_SLAVE_VENUS_CFG, MSM8916_SLAVE_CAMERA_CFG, MSM8916_SLAVE_DISPLAY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DEFINE_QNODE(pcnoc_s_8, MSM8916_PNOC_SLV_8, 4, -1, -1, MSM8916_SLAVE_USB_HS, MSM8916_SLAVE_SDCC_1, MSM8916_SLAVE_BLSP_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DEFINE_QNODE(pcnoc_s_9, MSM8916_PNOC_SLV_9, 4, -1, -1, MSM8916_SLAVE_SDCC_2, MSM8916_SLAVE_LPASS, MSM8916_SLAVE_GRAPHICS_3D_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DEFINE_QNODE(pcnoc_snoc_mas, MSM8916_PNOC_SNOC_MAS, 8, 29, -1, MSM8916_PNOC_SNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DEFINE_QNODE(pcnoc_snoc_slv, MSM8916_PNOC_SNOC_SLV, 8, -1, 45, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC, MSM8916_SNOC_INT_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DEFINE_QNODE(qdss_int, MSM8916_SNOC_QDSS_INT, 8, -1, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DEFINE_QNODE(slv_apps_l2, MSM8916_SLAVE_AMPSS_L2, 8, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DEFINE_QNODE(slv_apss, MSM8916_SLAVE_APSS, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DEFINE_QNODE(slv_audio, MSM8916_SLAVE_LPASS, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DEFINE_QNODE(slv_bimc_cfg, MSM8916_SLAVE_BIMC_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DEFINE_QNODE(slv_blsp_1, MSM8916_SLAVE_BLSP_1, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DEFINE_QNODE(slv_boot_rom, MSM8916_SLAVE_BOOT_ROM, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DEFINE_QNODE(slv_camera_cfg, MSM8916_SLAVE_CAMERA_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DEFINE_QNODE(slv_cats_0, MSM8916_SLAVE_CATS_128, 16, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DEFINE_QNODE(slv_cats_1, MSM8916_SLAVE_OCMEM_64, 8, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DEFINE_QNODE(slv_clk_ctl, MSM8916_SLAVE_CLK_CTL, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DEFINE_QNODE(slv_crypto_0_cfg, MSM8916_SLAVE_CRYPTO_0_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DEFINE_QNODE(slv_dehr_cfg, MSM8916_SLAVE_DEHR_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DEFINE_QNODE(slv_display_cfg, MSM8916_SLAVE_DISPLAY_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DEFINE_QNODE(slv_ebi_ch0, MSM8916_SLAVE_EBI_CH0, 8, -1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DEFINE_QNODE(slv_gfx_cfg, MSM8916_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DEFINE_QNODE(slv_imem_cfg, MSM8916_SLAVE_IMEM_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DEFINE_QNODE(slv_imem, MSM8916_SLAVE_IMEM, 8, -1, 26, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DEFINE_QNODE(slv_mpm, MSM8916_SLAVE_MPM, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DEFINE_QNODE(slv_msg_ram, MSM8916_SLAVE_MSG_RAM, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DEFINE_QNODE(slv_mss, MSM8916_SLAVE_MSS, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DEFINE_QNODE(slv_pdm, MSM8916_SLAVE_PDM, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DEFINE_QNODE(slv_pmic_arb, MSM8916_SLAVE_PMIC_ARB, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) DEFINE_QNODE(slv_pcnoc_cfg, MSM8916_SLAVE_PNOC_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) DEFINE_QNODE(slv_prng, MSM8916_SLAVE_PRNG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DEFINE_QNODE(slv_qdss_cfg, MSM8916_SLAVE_QDSS_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DEFINE_QNODE(slv_qdss_stm, MSM8916_SLAVE_QDSS_STM, 4, -1, 30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DEFINE_QNODE(slv_rbcpr_cfg, MSM8916_SLAVE_RBCPR_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) DEFINE_QNODE(slv_sdcc_1, MSM8916_SLAVE_SDCC_1, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DEFINE_QNODE(slv_sdcc_2, MSM8916_SLAVE_SDCC_2, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) DEFINE_QNODE(slv_security, MSM8916_SLAVE_SECURITY, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DEFINE_QNODE(slv_snoc_cfg, MSM8916_SLAVE_SNOC_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DEFINE_QNODE(slv_spdm, MSM8916_SLAVE_SPDM, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DEFINE_QNODE(slv_srvc_snoc, MSM8916_SLAVE_SRVC_SNOC, 8, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DEFINE_QNODE(slv_tcsr, MSM8916_SLAVE_TCSR, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DEFINE_QNODE(slv_tlmm, MSM8916_SLAVE_TLMM, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DEFINE_QNODE(slv_usb_hs, MSM8916_SLAVE_USB_HS, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) DEFINE_QNODE(slv_venus_cfg, MSM8916_SLAVE_VENUS_CFG, 4, -1, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DEFINE_QNODE(snoc_bimc_0_mas, MSM8916_SNOC_BIMC_0_MAS, 8, 3, -1, MSM8916_SNOC_BIMC_0_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) DEFINE_QNODE(snoc_bimc_0_slv, MSM8916_SNOC_BIMC_0_SLV, 8, -1, 24, MSM8916_SLAVE_EBI_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DEFINE_QNODE(snoc_bimc_1_mas, MSM8916_SNOC_BIMC_1_MAS, 16, -1, -1, MSM8916_SNOC_BIMC_1_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DEFINE_QNODE(snoc_bimc_1_slv, MSM8916_SNOC_BIMC_1_SLV, 8, -1, -1, MSM8916_SLAVE_EBI_CH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DEFINE_QNODE(snoc_int_0, MSM8916_SNOC_INT_0, 8, 99, 130, MSM8916_SLAVE_QDSS_STM, MSM8916_SLAVE_IMEM, MSM8916_SNOC_PNOC_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DEFINE_QNODE(snoc_int_1, MSM8916_SNOC_INT_1, 8, -1, -1, MSM8916_SLAVE_APSS, MSM8916_SLAVE_CATS_128, MSM8916_SLAVE_OCMEM_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DEFINE_QNODE(snoc_int_bimc, MSM8916_SNOC_INT_BIMC, 8, 101, 132, MSM8916_SNOC_BIMC_0_MAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DEFINE_QNODE(snoc_pcnoc_mas, MSM8916_SNOC_PNOC_MAS, 8, -1, -1, MSM8916_SNOC_PNOC_SLV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DEFINE_QNODE(snoc_pcnoc_slv, MSM8916_SNOC_PNOC_SLV, 8, -1, -1, MSM8916_PNOC_INT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct msm8916_icc_node *msm8916_snoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [BIMC_SNOC_SLV] = &bimc_snoc_slv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [MASTER_JPEG] = &mas_jpeg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [MASTER_MDP_PORT0] = &mas_mdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [MASTER_QDSS_BAM] = &mas_qdss_bam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [MASTER_QDSS_ETR] = &mas_qdss_etr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [MASTER_SNOC_CFG] = &mas_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [MASTER_VFE] = &mas_vfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [MASTER_VIDEO_P0] = &mas_video,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) [SNOC_MM_INT_0] = &mm_int_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [SNOC_MM_INT_1] = &mm_int_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [SNOC_MM_INT_2] = &mm_int_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [SNOC_MM_INT_BIMC] = &mm_int_bimc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [PCNOC_SNOC_SLV] = &pcnoc_snoc_slv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [SLAVE_APSS] = &slv_apss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [SLAVE_CATS_128] = &slv_cats_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [SLAVE_OCMEM_64] = &slv_cats_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [SLAVE_IMEM] = &slv_imem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [SLAVE_QDSS_STM] = &slv_qdss_stm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [SNOC_INT_0] = &snoc_int_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [SNOC_INT_1] = &snoc_int_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [SNOC_INT_BIMC] = &snoc_int_bimc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [SNOC_PCNOC_MAS] = &snoc_pcnoc_mas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [SNOC_QDSS_INT] = &qdss_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct msm8916_icc_desc msm8916_snoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .nodes = msm8916_snoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct msm8916_icc_node *msm8916_bimc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [BIMC_SNOC_MAS] = &bimc_snoc_mas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [MASTER_AMPSS_M0] = &mas_apss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [MASTER_GRAPHICS_3D] = &mas_gfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [MASTER_TCU0] = &mas_tcu0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [MASTER_TCU1] = &mas_tcu1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [SLAVE_AMPSS_L2] = &slv_apps_l2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [SLAVE_EBI_CH0] = &slv_ebi_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct msm8916_icc_desc msm8916_bimc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .nodes = msm8916_bimc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct msm8916_icc_node *msm8916_pcnoc_nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [MASTER_BLSP_1] = &mas_blsp_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [MASTER_DEHR] = &mas_dehr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [MASTER_LPASS] = &mas_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [MASTER_CRYPTO_CORE0] = &mas_pcnoc_crypto_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [MASTER_SDCC_1] = &mas_pcnoc_sdcc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [MASTER_SDCC_2] = &mas_pcnoc_sdcc_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [MASTER_SPDM] = &mas_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [MASTER_USB_HS] = &mas_usb_hs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [PCNOC_INT_0] = &pcnoc_int_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [PCNOC_INT_1] = &pcnoc_int_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [PCNOC_MAS_0] = &pcnoc_m_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [PCNOC_MAS_1] = &pcnoc_m_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [PCNOC_SLV_0] = &pcnoc_s_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [PCNOC_SLV_1] = &pcnoc_s_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [PCNOC_SLV_2] = &pcnoc_s_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [PCNOC_SLV_3] = &pcnoc_s_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [PCNOC_SLV_4] = &pcnoc_s_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [PCNOC_SLV_8] = &pcnoc_s_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [PCNOC_SLV_9] = &pcnoc_s_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [PCNOC_SNOC_MAS] = &pcnoc_snoc_mas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [SLAVE_BLSP_1] = &slv_blsp_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [SLAVE_BOOT_ROM] = &slv_boot_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [SLAVE_CLK_CTL] = &slv_clk_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [SLAVE_DEHR_CFG] = &slv_dehr_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [SLAVE_IMEM_CFG] = &slv_imem_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [SLAVE_LPASS] = &slv_audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [SLAVE_MPM] = &slv_mpm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [SLAVE_MSG_RAM] = &slv_msg_ram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [SLAVE_MSS] = &slv_mss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [SLAVE_PDM] = &slv_pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [SLAVE_PMIC_ARB] = &slv_pmic_arb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [SLAVE_PCNOC_CFG] = &slv_pcnoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [SLAVE_PRNG] = &slv_prng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) [SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [SLAVE_SDCC_1] = &slv_sdcc_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [SLAVE_SDCC_2] = &slv_sdcc_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [SLAVE_SECURITY] = &slv_security,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [SLAVE_SPDM] = &slv_spdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [SLAVE_TCSR] = &slv_tcsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [SLAVE_TLMM] = &slv_tlmm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [SLAVE_USB_HS] = &slv_usb_hs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [SLAVE_VENUS_CFG] = &slv_venus_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct msm8916_icc_desc msm8916_pcnoc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .nodes = msm8916_pcnoc_nodes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int msm8916_icc_set(struct icc_node *src, struct icc_node *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct msm8916_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct msm8916_icc_node *qn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u64 sum_bw, max_peak_bw, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 agg_avg = 0, agg_peak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct icc_node *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) qn = src->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) provider = src->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) qp = to_msm8916_provider(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) list_for_each_entry(n, &provider->nodes, node_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) &agg_avg, &agg_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) sum_bw = icc_units_to_bps(agg_avg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) max_peak_bw = icc_units_to_bps(agg_peak);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* send bandwidth request message to the RPM processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (qn->mas_rpm_id != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RPM_BUS_MASTER_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) qn->mas_rpm_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sum_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) qn->mas_rpm_id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (qn->slv_rpm_id != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) RPM_BUS_SLAVE_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) qn->slv_rpm_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) sum_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pr_err("qcom_icc_rpm_smd_send slv error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) rate = max(sum_bw, max_peak_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) do_div(rate, qn->buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (qn->rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (i = 0; i < qp->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = clk_set_rate(qp->bus_clks[i].clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pr_err("%s clk_set_rate error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) qp->bus_clks[i].id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) qn->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int msm8916_qnoc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) const struct msm8916_icc_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct msm8916_icc_node **qnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct msm8916_icc_provider *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct icc_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct icc_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct icc_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) size_t num_nodes, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* wait for the RPM proxy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!qcom_icc_rpm_smd_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) desc = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) qnodes = desc->nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) num_nodes = desc->num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) qp->bus_clks = devm_kmemdup(dev, msm8916_bus_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sizeof(msm8916_bus_clocks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!qp->bus_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) qp->num_clks = ARRAY_SIZE(msm8916_bus_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) provider = &qp->provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) INIT_LIST_HEAD(&provider->nodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) provider->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) provider->set = msm8916_icc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) provider->aggregate = icc_std_aggregate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) provider->xlate = of_icc_xlate_onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) provider->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = icc_provider_add(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(dev, "error adding interconnect provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) for (i = 0; i < num_nodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) size_t j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) node = icc_node_create(qnodes[i]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (IS_ERR(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = PTR_ERR(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) node->name = qnodes[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) node->data = qnodes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) icc_node_add(node, provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (j = 0; j < qnodes[i]->num_links; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) icc_link_create(node, qnodes[i]->links[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) data->nodes[i] = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) data->num_nodes = num_nodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) platform_set_drvdata(pdev, qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) icc_nodes_remove(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) icc_provider_del(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int msm8916_qnoc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct msm8916_icc_provider *qp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) icc_nodes_remove(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return icc_provider_del(&qp->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct of_device_id msm8916_noc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { .compatible = "qcom,msm8916-pcnoc", .data = &msm8916_pcnoc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .compatible = "qcom,msm8916-snoc", .data = &msm8916_snoc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_DEVICE_TABLE(of, msm8916_noc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static struct platform_driver msm8916_noc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .probe = msm8916_qnoc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .remove = msm8916_qnoc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .name = "qnoc-msm8916",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .of_match_table = msm8916_noc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) module_platform_driver(msm8916_noc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_DESCRIPTION("Qualcomm MSM8916 NoC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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