^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Interconnect framework driver for i.MX8MQ SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019-2020, NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interconnect-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/interconnect/imx8mq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct imx_icc_node_adj_desc imx8mq_dram_adj = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .bw_mul = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .bw_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .phandle_name = "fsl,ddrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct imx_icc_node_adj_desc imx8mq_noc_adj = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .bw_mul = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .bw_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .main_noc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Describe bus masters, slaves and connections between them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * This is a simplified subset of the bus diagram, there are several other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * PL301 nics which are skipped/merged into PL301_MAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct imx_icc_node_desc nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_BUS_INTERCONNECT("NOC", IMX8MQ_ICN_NOC, &imx8mq_noc_adj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) IMX8MQ_ICS_DRAM, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_BUS_SLAVE("DRAM", IMX8MQ_ICS_DRAM, &imx8mq_dram_adj),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_BUS_SLAVE("OCRAM", IMX8MQ_ICS_OCRAM, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_BUS_MASTER("A53", IMX8MQ_ICM_A53, IMX8MQ_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* VPUMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_BUS_MASTER("VPU", IMX8MQ_ICM_VPU, IMX8MQ_ICN_VIDEO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MQ_ICN_VIDEO, NULL, IMX8MQ_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* GPUMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_BUS_MASTER("GPU", IMX8MQ_ICM_GPU, IMX8MQ_ICN_GPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MQ_ICN_GPU, NULL, IMX8MQ_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* DISPMIX (only for DCSS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_BUS_MASTER("DC", IMX8MQ_ICM_DCSS, IMX8MQ_ICN_DCSS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_BUS_INTERCONNECT("PL301_DC", IMX8MQ_ICN_DCSS, NULL, IMX8MQ_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* USBMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEFINE_BUS_MASTER("USB1", IMX8MQ_ICM_USB1, IMX8MQ_ICN_USB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_BUS_MASTER("USB2", IMX8MQ_ICM_USB2, IMX8MQ_ICN_USB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_BUS_INTERCONNECT("PL301_USB", IMX8MQ_ICN_USB, NULL, IMX8MQ_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* PL301_DISPLAY (IPs other than DCSS, inside SUPERMIX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_BUS_MASTER("CSI1", IMX8MQ_ICM_CSI1, IMX8MQ_ICN_DISPLAY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_BUS_MASTER("CSI2", IMX8MQ_ICM_CSI2, IMX8MQ_ICN_DISPLAY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_BUS_MASTER("LCDIF", IMX8MQ_ICM_LCDIF, IMX8MQ_ICN_DISPLAY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_BUS_INTERCONNECT("PL301_DISPLAY", IMX8MQ_ICN_DISPLAY, NULL, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* AUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_BUS_MASTER("SDMA2", IMX8MQ_ICM_SDMA2, IMX8MQ_ICN_AUDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MQ_ICN_AUDIO, NULL, IMX8MQ_ICN_DISPLAY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* ENET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEFINE_BUS_MASTER("ENET", IMX8MQ_ICM_ENET, IMX8MQ_ICN_ENET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MQ_ICN_ENET, NULL, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* OTHER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEFINE_BUS_MASTER("SDMA1", IMX8MQ_ICM_SDMA1, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEFINE_BUS_MASTER("NAND", IMX8MQ_ICM_NAND, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE_BUS_MASTER("USDHC1", IMX8MQ_ICM_USDHC1, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEFINE_BUS_MASTER("USDHC2", IMX8MQ_ICM_USDHC2, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE_BUS_MASTER("PCIE1", IMX8MQ_ICM_PCIE1, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEFINE_BUS_MASTER("PCIE2", IMX8MQ_ICM_PCIE2, IMX8MQ_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MQ_ICN_MAIN, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) IMX8MQ_ICN_NOC, IMX8MQ_ICS_OCRAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int imx8mq_icc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int imx8mq_icc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return imx_icc_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct platform_driver imx8mq_icc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .probe = imx8mq_icc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .remove = imx8mq_icc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .name = "imx8mq-interconnect",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .sync_state = icc_sync_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) module_platform_driver(imx8mq_icc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_ALIAS("platform:imx8mq-interconnect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_AUTHOR("Leonard Crestez <leonard.crestez@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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