^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Interconnect framework driver for i.MX8MN SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019-2020, NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/interconnect/imx8mn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct imx_icc_node_adj_desc imx8mn_dram_adj = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .bw_mul = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .bw_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .phandle_name = "fsl,ddrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct imx_icc_node_adj_desc imx8mn_noc_adj = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .bw_mul = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .bw_div = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .main_noc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Describe bus masters, slaves and connections between them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This is a simplified subset of the bus diagram, there are several other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * PL301 nics which are skipped/merged into PL301_MAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct imx_icc_node_desc nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_BUS_INTERCONNECT("NOC", IMX8MN_ICN_NOC, &imx8mn_noc_adj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) IMX8MN_ICS_DRAM, IMX8MN_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_BUS_SLAVE("DRAM", IMX8MN_ICS_DRAM, &imx8mn_dram_adj),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_BUS_SLAVE("OCRAM", IMX8MN_ICS_OCRAM, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_BUS_MASTER("A53", IMX8MN_ICM_A53, IMX8MN_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* GPUMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_BUS_MASTER("GPU", IMX8MN_ICM_GPU, IMX8MN_ICN_GPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MN_ICN_GPU, NULL, IMX8MN_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* DISPLAYMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_BUS_MASTER("CSI1", IMX8MN_ICM_CSI1, IMX8MN_ICN_MIPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_BUS_MASTER("CSI2", IMX8MN_ICM_CSI2, IMX8MN_ICN_MIPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_BUS_MASTER("ISI", IMX8MN_ICM_ISI, IMX8MN_ICN_MIPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_BUS_MASTER("LCDIF", IMX8MN_ICM_LCDIF, IMX8MN_ICN_MIPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MN_ICN_MIPI, NULL, IMX8MN_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* USB goes straight to NOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_BUS_MASTER("USB", IMX8MN_ICM_USB, IMX8MN_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_BUS_MASTER("SDMA2", IMX8MN_ICM_SDMA2, IMX8MN_ICN_AUDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_BUS_MASTER("SDMA3", IMX8MN_ICM_SDMA3, IMX8MN_ICN_AUDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MN_ICN_AUDIO, NULL, IMX8MN_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_BUS_MASTER("ENET", IMX8MN_ICM_ENET, IMX8MN_ICN_ENET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MN_ICN_ENET, NULL, IMX8MN_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Other */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEFINE_BUS_MASTER("SDMA1", IMX8MN_ICM_SDMA1, IMX8MN_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_BUS_MASTER("NAND", IMX8MN_ICM_NAND, IMX8MN_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_BUS_MASTER("USDHC1", IMX8MN_ICM_USDHC1, IMX8MN_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE_BUS_MASTER("USDHC2", IMX8MN_ICM_USDHC2, IMX8MN_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEFINE_BUS_MASTER("USDHC3", IMX8MN_ICM_USDHC3, IMX8MN_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MN_ICN_MAIN, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) IMX8MN_ICN_NOC, IMX8MN_ICS_OCRAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int imx8mn_icc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int imx8mn_icc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return imx_icc_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct platform_driver imx8mn_icc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .probe = imx8mn_icc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .remove = imx8mn_icc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = "imx8mn-interconnect",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) module_platform_driver(imx8mn_icc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_ALIAS("platform:imx8mn-interconnect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MODULE_AUTHOR("Leonard Crestez <leonard.crestez@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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