^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Interconnect framework driver for i.MX8MM SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019, BayLibre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2019-2020, NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Alexandre Bailon <abailon@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Leonard Crestez <leonard.crestez@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/interconnect/imx8mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const struct imx_icc_node_adj_desc imx8mm_dram_adj = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .bw_mul = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .bw_div = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .phandle_name = "fsl,ddrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const struct imx_icc_node_adj_desc imx8mm_noc_adj = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .bw_mul = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .bw_div = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .main_noc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Describe bus masters, slaves and connections between them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This is a simplified subset of the bus diagram, there are several other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * PL301 nics which are skipped/merged into PL301_MAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct imx_icc_node_desc nodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* VPUMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* GPUMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* DISPLAYMIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* HSIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Other */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int imx8mm_icc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int imx8mm_icc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return imx_icc_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct platform_driver imx8mm_icc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .probe = imx8mm_icc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .remove = imx8mm_icc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "imx8mm-interconnect",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) module_platform_driver(imx8mm_icc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_AUTHOR("Alexandre Bailon <abailon@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MODULE_ALIAS("platform:imx8mm-interconnect");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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