Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * wm9705.c  --  Codec driver for Wolfson WM9705 AC97 Codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2003, 2004, 2005, 2006, 2007 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Parts Copyright : Ian Molton <spyro@f2s.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *                   Andrew Zabolotny <zap@homelink.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *                   Russell King <rmk@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/wm97xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TS_NAME			"wm97xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define WM9705_VERSION		"1.00"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DEFAULT_PRESSURE	0xb0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Module parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Set current used for pressure measurement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * Set pil = 2 to use 400uA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *     pil = 1 to use 200uA and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *     pil = 0 to disable pressure measurement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * This is used to increase the range of values returned by the adc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * when measureing touchpanel pressure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static int pil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) module_param(pil, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) MODULE_PARM_DESC(pil, "Set current used for pressure measurement.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * Set threshold for pressure measurement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * Pen down pressure below threshold is ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static int pressure = DEFAULT_PRESSURE & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) module_param(pressure, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) MODULE_PARM_DESC(pressure, "Set threshold for pressure measurement.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * Set adc sample delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * For accurate touchpanel measurements, some settling time may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * required between the switch matrix applying a voltage across the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * touchpanel plate and the ADC sampling the signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * This delay can be set by setting delay = n, where n is the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * position of the delay in the array delay_table below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * Long delays > 1ms are supported for completeness, but are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * recommended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static int delay = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) module_param(delay, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) MODULE_PARM_DESC(delay, "Set adc sample delay.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * Pen detect comparator threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * 0 to Vmid in 15 steps, 0 = use zero power comparator with Vmid threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * i.e. 1 =  Vmid/15 threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *      15 =  Vmid/1 threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * Adjust this value if you are having problems with pen detect not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * detecting any down events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int pdd = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) module_param(pdd, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) MODULE_PARM_DESC(pdd, "Set pen detect comparator threshold");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * Set adc mask function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * Sources of glitch noise, such as signals driving an LCD display, may feed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * through to the touch screen plates and affect measurement accuracy. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * order to minimise this, a signal may be applied to the MASK pin to delay or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * synchronise the sampling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * 0 = No delay or sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * 1 = High on pin stops conversions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * 2 = Edge triggered, edge on pin delays conversion by delay param (above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * 3 = Edge triggered, edge on pin starts conversion after delay param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) module_param(mask, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) MODULE_PARM_DESC(mask, "Set adc mask function.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * ADC sample delay times in uS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const int delay_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	21,    /* 1 AC97 Link frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	42,    /* 2                  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	84,    /* 4                  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	167,   /* 8                  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	333,   /* 16                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	667,   /* 32                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	1000,  /* 48                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	1333,  /* 64                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	2000,  /* 96                 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	2667,  /* 128                */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	3333,  /* 160                */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	4000,  /* 192                */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	4667,  /* 224                */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	5333,  /* 256                */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	6000,  /* 288                */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	0      /* No delay, switch matrix always on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * Delay after issuing a POLL command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * The delay is 3 AC97 link frames + the touchpanel settling delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void poll_delay(int d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	udelay(3 * AC97_LINK_FRAME + delay_table[d]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * set up the physical settings of the WM9705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void wm9705_phy_init(struct wm97xx *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u16 dig1 = 0, dig2 = WM97XX_RPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	* mute VIDEO and AUX as they share X and Y touchscreen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	* inputs on the WM9705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	wm97xx_reg_write(wm, AC97_AUX, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	wm97xx_reg_write(wm, AC97_VIDEO, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* touchpanel pressure current*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (pil == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		dig2 |= WM9705_PIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		dev_dbg(wm->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			"setting pressure measurement current to 400uA.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	} else if (pil)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		dev_dbg(wm->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			"setting pressure measurement current to 200uA.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!pil)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		pressure = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* polling mode sample settling delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (delay != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (delay < 0 || delay > 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			dev_dbg(wm->dev, "supplied delay out of range.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			delay = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	dig1 &= 0xff0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	dig1 |= WM97XX_DELAY(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	dev_dbg(wm->dev, "setting adc sample delay to %d u Secs.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		delay_table[delay]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* WM9705 pdd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	dig2 |= (pdd & 0x000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	dev_dbg(wm->dev, "setting pdd to Vmid/%d", 1 - (pdd & 0x000f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	dig2 |= ((mask & 0x3) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void wm9705_dig_enable(struct wm97xx *wm, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				 wm->dig[2] | WM97XX_PRP_DET_DIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				 wm->dig[2] & ~WM97XX_PRP_DET_DIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void wm9705_aux_prepare(struct wm97xx *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	memcpy(wm->dig_save, wm->dig, sizeof(wm->dig));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, WM97XX_PRP_DET_DIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void wm9705_dig_restore(struct wm97xx *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, wm->dig_save[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm->dig_save[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline int is_pden(struct wm97xx *wm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return wm->dig[2] & WM9705_PDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * Read a sample from the WM9705 adc in polling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int wm9705_poll_sample(struct wm97xx *wm, int adcsel, int *sample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int timeout = 5 * delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	bool wants_pen = adcsel & WM97XX_PEN_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (wants_pen && !wm->pen_probably_down) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		u16 data = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		if (!(data & WM97XX_PEN_DOWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			return RC_PENUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		wm->pen_probably_down = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* set up digitiser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (wm->mach_ops && wm->mach_ops->pre_sample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		wm->mach_ops->pre_sample(adcsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, (adcsel & WM97XX_ADCSEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				| WM97XX_POLL | WM97XX_DELAY(delay));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* wait 3 AC97 time slots + delay for conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	poll_delay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* wait for POLL to go low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	while ((wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER1) & WM97XX_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	       && timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		udelay(AC97_LINK_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		/* If PDEN is set, we can get a timeout when pen goes up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (is_pden(wm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			wm->pen_probably_down = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			dev_dbg(wm->dev, "adc sample timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return RC_PENUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	*sample = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (wm->mach_ops && wm->mach_ops->post_sample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		wm->mach_ops->post_sample(adcsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* check we have correct sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if ((*sample ^ adcsel) & WM97XX_ADCSEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		dev_dbg(wm->dev, "adc wrong sample, wanted %x got %x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			adcsel & WM97XX_ADCSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			*sample & WM97XX_ADCSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return RC_PENUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (wants_pen && !(*sample & WM97XX_PEN_DOWN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		wm->pen_probably_down = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return RC_PENUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return RC_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  * Sample the WM9705 touchscreen in polling mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int wm9705_poll_touch(struct wm97xx *wm, struct wm97xx_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_X | WM97XX_PEN_DOWN, &data->x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (rc != RC_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_Y | WM97XX_PEN_DOWN, &data->y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (rc != RC_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (pil) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_PRES | WM97XX_PEN_DOWN, &data->p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		if (rc != RC_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		data->p = DEFAULT_PRESSURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return RC_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  * Enable WM9705 continuous mode, i.e. touch data is streamed across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  * an AC97 slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int wm9705_acc_enable(struct wm97xx *wm, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	u16 dig1, dig2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	dig1 = wm->dig[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	dig2 = wm->dig[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		/* continuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		if (wm->mach_ops->acc_startup &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		    (ret = wm->mach_ops->acc_startup(wm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		dig1 &= ~(WM97XX_CM_RATE_MASK | WM97XX_ADCSEL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			  WM97XX_DELAY_MASK | WM97XX_SLT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		dig1 |= WM97XX_CTC | WM97XX_COO | WM97XX_SLEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			WM97XX_DELAY(delay) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			WM97XX_SLT(wm->acc_slot) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			WM97XX_RATE(wm->acc_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		if (pil)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			dig1 |= WM97XX_ADCSEL_PRES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		dig2 |= WM9705_PDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		dig1 &= ~(WM97XX_CTC | WM97XX_COO | WM97XX_SLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		dig2 &= ~WM9705_PDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (wm->mach_ops->acc_shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			wm->mach_ops->acc_shutdown(wm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct wm97xx_codec_drv wm9705_codec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.id = WM9705_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.name = "wm9705",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.poll_sample = wm9705_poll_sample,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.poll_touch = wm9705_poll_touch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.acc_enable = wm9705_acc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.phy_init = wm9705_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.dig_enable = wm9705_dig_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.dig_restore = wm9705_dig_restore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.aux_prepare = wm9705_aux_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) EXPORT_SYMBOL_GPL(wm9705_codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_AUTHOR("Liam Girdwood <lrg@slimlogic.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_DESCRIPTION("WM9705 Touch Screen Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_LICENSE("GPL");