Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Philips UCB1400 touchscreen driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Author:	Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Created:	September 25, 2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright:	MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Spliting done by: Marek Vasut <marek.vasut@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * If something doesn't work and it worked before spliting, e-mail me,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * dont bother Nicolas please ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This code is heavily based on ucb1x00-*.c copyrighted by Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * covering the UCB1100, UCB1200 and UCB1300..  Support for the UCB1400 has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * been made separate from ucb1x00-core/ucb1x00-ts on Russell's request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/ucb1400.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define UCB1400_TS_POLL_PERIOD	10 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static bool adcsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static int ts_delay = 55; /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int ts_delay_pressure;	/* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Switch to interrupt mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void ucb1400_ts_mode_int(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			UCB_TS_CR_MODE_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * Switch to pressure mode, and read pressure.  We don't need to wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * here, since both plates are being driven.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static unsigned int ucb1400_ts_read_pressure(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	udelay(ts_delay_pressure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return ucb1400_adc_read(ucb->ac97, UCB_ADC_INP_TSPY, adcsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * Switch to X position mode and measure Y plate.  We switch the plate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * configuration in pressure mode, then switch to position mode.  This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * gives a faster response time.  Even so, we need to wait about 55us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * for things to stabilise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static unsigned int ucb1400_ts_read_xpos(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	udelay(ts_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return ucb1400_adc_read(ucb->ac97, UCB_ADC_INP_TSPY, adcsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * Switch to Y position mode and measure X plate.  We switch the plate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * configuration in pressure mode, then switch to position mode.  This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * gives a faster response time.  Even so, we need to wait about 55us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * for things to stabilise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int ucb1400_ts_read_ypos(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	udelay(ts_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return ucb1400_adc_read(ucb->ac97, UCB_ADC_INP_TSPX, adcsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * Switch to X plate resistance mode.  Set MX to ground, PX to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * supply.  Measure current.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static unsigned int ucb1400_ts_read_xres(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return ucb1400_adc_read(ucb->ac97, 0, adcsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * Switch to Y plate resistance mode.  Set MY to ground, PY to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * supply.  Measure current.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static unsigned int ucb1400_ts_read_yres(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return ucb1400_adc_read(ucb->ac97, 0, adcsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int ucb1400_ts_pen_up(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned short val = ucb1400_reg_read(ucb->ac97, UCB_TS_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void ucb1400_ts_irq_enable(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, UCB_IE_TSPX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ucb1400_reg_write(ucb->ac97, UCB_IE_FAL, UCB_IE_TSPX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void ucb1400_ts_irq_disable(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ucb1400_reg_write(ucb->ac97, UCB_IE_FAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void ucb1400_ts_report_event(struct input_dev *idev, u16 pressure, u16 x, u16 y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	input_report_abs(idev, ABS_X, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	input_report_abs(idev, ABS_Y, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	input_report_abs(idev, ABS_PRESSURE, pressure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	input_report_key(idev, BTN_TOUCH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	input_sync(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void ucb1400_ts_event_release(struct input_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	input_report_abs(idev, ABS_PRESSURE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	input_report_key(idev, BTN_TOUCH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	input_sync(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void ucb1400_clear_pending_irq(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned int isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	isr = ucb1400_reg_read(ucb->ac97, UCB_IE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (isr & UCB_IE_TSPX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ucb1400_ts_irq_disable(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		dev_dbg(&ucb->ts_idev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			"ucb1400: unexpected IE_STATUS = %#x\n", isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * A restriction with interrupts exists when using the ucb1400, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * the codec read/write routines may sleep while waiting for codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * access completion and uses semaphores for access control to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * AC97 bus. Therefore the driver is forced to use threaded interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  * handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static irqreturn_t ucb1400_irq(int irqnr, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct ucb1400_ts *ucb = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	unsigned int x, y, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	bool penup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (unlikely(irqnr != ucb->irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ucb1400_clear_pending_irq(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* Start with a small delay before checking pendown state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	msleep(UCB1400_TS_POLL_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	while (!ucb->stopped && !(penup = ucb1400_ts_pen_up(ucb))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		ucb1400_adc_enable(ucb->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		x = ucb1400_ts_read_xpos(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		y = ucb1400_ts_read_ypos(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		p = ucb1400_ts_read_pressure(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		ucb1400_adc_disable(ucb->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		ucb1400_ts_report_event(ucb->ts_idev, p, x, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		wait_event_timeout(ucb->ts_wait, ucb->stopped,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				   msecs_to_jiffies(UCB1400_TS_POLL_PERIOD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ucb1400_ts_event_release(ucb->ts_idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (!ucb->stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		/* Switch back to interrupt mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		ucb1400_ts_mode_int(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		ucb1400_ts_irq_enable(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void ucb1400_ts_stop(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* Signal IRQ thread to stop polling and disable the handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ucb->stopped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	wake_up(&ucb->ts_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	disable_irq(ucb->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ucb1400_ts_irq_disable(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ucb1400_reg_write(ucb->ac97, UCB_TS_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Must be called with ts->lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void ucb1400_ts_start(struct ucb1400_ts *ucb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* Tell IRQ thread that it may poll the device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ucb->stopped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ucb1400_ts_mode_int(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ucb1400_ts_irq_enable(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	enable_irq(ucb->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int ucb1400_ts_open(struct input_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct ucb1400_ts *ucb = input_get_drvdata(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ucb1400_ts_start(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void ucb1400_ts_close(struct input_dev *idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct ucb1400_ts *ucb = input_get_drvdata(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ucb1400_ts_stop(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #ifndef NO_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define NO_IRQ	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * Try to probe our interrupt, rather than relying on lots of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * hard-coded machine dependencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int ucb1400_ts_detect_irq(struct ucb1400_ts *ucb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 					   struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	unsigned long mask, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	mask = probe_irq_on();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	/* Enable the ADC interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	ucb1400_reg_write(ucb->ac97, UCB_IE_RIS, UCB_IE_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ucb1400_reg_write(ucb->ac97, UCB_IE_FAL, UCB_IE_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* Cause an ADC interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	ucb1400_reg_write(ucb->ac97, UCB_ADC_CR, UCB_ADC_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ucb1400_reg_write(ucb->ac97, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Wait for the conversion to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	timeout = jiffies + HZ/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	while (!(ucb1400_reg_read(ucb->ac97, UCB_ADC_DATA) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 						UCB_ADC_DAT_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			dev_err(&pdev->dev, "timed out in IRQ probe\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			probe_irq_off(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ucb1400_reg_write(ucb->ac97, UCB_ADC_CR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	/* Disable and clear interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	ucb1400_reg_write(ucb->ac97, UCB_IE_RIS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ucb1400_reg_write(ucb->ac97, UCB_IE_FAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	/* Read triggered interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	ucb->irq = probe_irq_off(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (ucb->irq < 0 || ucb->irq == NO_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int ucb1400_ts_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct ucb1400_ts *ucb = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	int error, x_res, y_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	u16 fcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	ucb->ts_idev = input_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (!ucb->ts_idev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/* Only in case the IRQ line wasn't supplied, try detecting it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (ucb->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		error = ucb1400_ts_detect_irq(ucb, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			dev_err(&pdev->dev, "IRQ probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			goto err_free_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	dev_dbg(&pdev->dev, "found IRQ %d\n", ucb->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	init_waitqueue_head(&ucb->ts_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	input_set_drvdata(ucb->ts_idev, ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	ucb->ts_idev->dev.parent	= &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ucb->ts_idev->name		= "UCB1400 touchscreen interface";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	ucb->ts_idev->id.vendor		= ucb1400_reg_read(ucb->ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 						AC97_VENDOR_ID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	ucb->ts_idev->id.product	= ucb->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	ucb->ts_idev->open		= ucb1400_ts_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ucb->ts_idev->close		= ucb1400_ts_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ucb->ts_idev->evbit[0]		= BIT_MASK(EV_ABS) | BIT_MASK(EV_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ucb->ts_idev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	 * Enable ADC filter to prevent horrible jitter on Colibri.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	 * This also further reduces jitter on boards where ADCSYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	 * pin is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	fcsr = ucb1400_reg_read(ucb->ac97, UCB_FCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	ucb1400_reg_write(ucb->ac97, UCB_FCSR, fcsr | UCB_FCSR_AVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	ucb1400_adc_enable(ucb->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	x_res = ucb1400_ts_read_xres(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	y_res = ucb1400_ts_read_yres(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	ucb1400_adc_disable(ucb->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	dev_dbg(&pdev->dev, "x/y = %d/%d\n", x_res, y_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	input_set_abs_params(ucb->ts_idev, ABS_X, 0, x_res, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	input_set_abs_params(ucb->ts_idev, ABS_Y, 0, y_res, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	input_set_abs_params(ucb->ts_idev, ABS_PRESSURE, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	ucb1400_ts_stop(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	error = request_threaded_irq(ucb->irq, NULL, ucb1400_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 				     IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 				     "UCB1400", ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			"unable to grab irq%d: %d\n", ucb->irq, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		goto err_free_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	error = input_register_device(ucb->ts_idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	free_irq(ucb->irq, ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) err_free_devs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	input_free_device(ucb->ts_idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int ucb1400_ts_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	struct ucb1400_ts *ucb = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	free_irq(ucb->irq, ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	input_unregister_device(ucb->ts_idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int __maybe_unused ucb1400_ts_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	struct ucb1400_ts *ucb = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	struct input_dev *idev = ucb->ts_idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	mutex_lock(&idev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (idev->users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		ucb1400_ts_stop(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	mutex_unlock(&idev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int __maybe_unused ucb1400_ts_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	struct ucb1400_ts *ucb = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	struct input_dev *idev = ucb->ts_idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	mutex_lock(&idev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (idev->users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		ucb1400_ts_start(ucb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	mutex_unlock(&idev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static SIMPLE_DEV_PM_OPS(ucb1400_ts_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 			 ucb1400_ts_suspend, ucb1400_ts_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static struct platform_driver ucb1400_ts_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.probe	= ucb1400_ts_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.remove	= ucb1400_ts_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		.name	= "ucb1400_ts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		.pm	= &ucb1400_ts_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) module_platform_driver(ucb1400_ts_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) module_param(adcsync, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_PARM_DESC(adcsync, "Synchronize touch readings with ADCSYNC pin.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) module_param(ts_delay, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_PARM_DESC(ts_delay, "Delay between panel setup and"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 			    " position read. Default = 55us.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) module_param(ts_delay_pressure, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_PARM_DESC(ts_delay_pressure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		"delay between panel setup and pressure read."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		"  Default = 0us.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MODULE_DESCRIPTION("Philips UCB1400 touchscreen driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MODULE_LICENSE("GPL");