^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Surface2.0/SUR40/PixelSense input driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 by Florian 'floe' Echtler <floe@butterbrot.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Derived from the USB Skeleton driver 1.1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2003 Greg Kroah-Hartman (greg@kroah.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * and from the Apple USB BCM5974 multitouch driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2008 Henrik Rydberg (rydberg@euromail.se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * and from the generic hid-multitouch driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (c) 2010-2012 Stephane Chatty <chatty@enac.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * and from the v4l2-pci-skeleton driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (c) Copyright 2014 Cisco Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/input/mt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/usb/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <media/videobuf2-v4l2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <media/videobuf2-dma-sg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* read 512 bytes from endpoint 0x86 -> get header + blobs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct sur40_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __le16 type; /* always 0x0001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __le16 count; /* count of blobs (if 0: continue prev. packet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __le32 packet_id; /* unique ID for all packets in one frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __le32 timestamp; /* milliseconds (inc. by 16 or 17 each frame) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __le32 unknown; /* "epoch?" always 02/03 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct sur40_blob {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __le16 blob_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 action; /* 0x02 = enter/exit, 0x03 = update (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 type; /* bitmask (0x01 blob, 0x02 touch, 0x04 tag) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __le16 bb_pos_x; /* upper left corner of bounding box */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __le16 bb_pos_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __le16 bb_size_x; /* size of bounding box */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __le16 bb_size_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __le16 pos_x; /* finger tip position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __le16 pos_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __le16 ctr_x; /* centroid position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __le16 ctr_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __le16 axis_x; /* somehow related to major/minor axis, mostly: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __le16 axis_y; /* axis_x == bb_size_y && axis_y == bb_size_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __le32 angle; /* orientation in radians relative to x axis -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) actually an IEEE754 float, don't use in kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __le32 area; /* size in pixels/pressure (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 padding[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __le32 tag_id; /* valid when type == 0x04 (SUR40_TAG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __le32 unknown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* combined header/blob data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct sur40_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct sur40_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct sur40_blob blobs[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* read 512 bytes from endpoint 0x82 -> get header below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * continue reading 16k blocks until header.size bytes read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct sur40_image_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __le32 magic; /* "SUBF" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __le32 packet_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __le32 size; /* always 0x0007e900 = 960x540 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __le32 timestamp; /* milliseconds (increases by 16 or 17 each frame) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __le32 unknown; /* "epoch?" always 02/03 00 00 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* version information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRIVER_SHORT "sur40"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRIVER_LONG "Samsung SUR40"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRIVER_AUTHOR "Florian 'floe' Echtler <floe@butterbrot.org>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRIVER_DESC "Surface2.0/SUR40/PixelSense input driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* vendor and device IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ID_MICROSOFT 0x045e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ID_SUR40 0x0775
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* sensor resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SENSOR_RES_X 1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SENSOR_RES_Y 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* touch data endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TOUCH_ENDPOINT 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* video data endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VIDEO_ENDPOINT 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* video header fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VIDEO_HEADER_MAGIC 0x46425553
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VIDEO_PACKET_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* polling interval (ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define POLL_INTERVAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* maximum number of contacts FIXME: this is a guess? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAX_CONTACTS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* control commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SUR40_GET_VERSION 0xb0 /* 12 bytes string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SUR40_ACCEL_CAPS 0xb3 /* 5 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SUR40_SENSOR_CAPS 0xc1 /* 24 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SUR40_POKE 0xc5 /* poke register byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SUR40_PEEK 0xc4 /* 48 bytes registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SUR40_GET_STATE 0xc5 /* 4 bytes state (?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SUR40_GET_SENSORS 0xb1 /* 8 bytes sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SUR40_BLOB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SUR40_TOUCH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SUR40_TAG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* video controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SUR40_BRIGHTNESS_MAX 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SUR40_BRIGHTNESS_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SUR40_BRIGHTNESS_DEF 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SUR40_CONTRAST_MAX 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SUR40_CONTRAST_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SUR40_CONTRAST_DEF 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SUR40_GAIN_MAX 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SUR40_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SUR40_GAIN_DEF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SUR40_BACKLIGHT_MAX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SUR40_BACKLIGHT_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SUR40_BACKLIGHT_DEF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define sur40_str(s) #s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SUR40_PARAM_RANGE(lo, hi) " (range " sur40_str(lo) "-" sur40_str(hi) ")"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static uint brightness = SUR40_BRIGHTNESS_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) module_param(brightness, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_PARM_DESC(brightness, "set initial brightness"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SUR40_PARAM_RANGE(SUR40_BRIGHTNESS_MIN, SUR40_BRIGHTNESS_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static uint contrast = SUR40_CONTRAST_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) module_param(contrast, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MODULE_PARM_DESC(contrast, "set initial contrast"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SUR40_PARAM_RANGE(SUR40_CONTRAST_MIN, SUR40_CONTRAST_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static uint gain = SUR40_GAIN_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) module_param(gain, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MODULE_PARM_DESC(gain, "set initial gain"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SUR40_PARAM_RANGE(SUR40_GAIN_MIN, SUR40_GAIN_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct v4l2_pix_format sur40_pix_format[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .pixelformat = V4L2_TCH_FMT_TU08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .width = SENSOR_RES_X / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .height = SENSOR_RES_Y / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .field = V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .colorspace = V4L2_COLORSPACE_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .bytesperline = SENSOR_RES_X / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .sizeimage = (SENSOR_RES_X/2) * (SENSOR_RES_Y/2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .pixelformat = V4L2_PIX_FMT_GREY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .width = SENSOR_RES_X / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .height = SENSOR_RES_Y / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .field = V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .colorspace = V4L2_COLORSPACE_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .bytesperline = SENSOR_RES_X / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .sizeimage = (SENSOR_RES_X/2) * (SENSOR_RES_Y/2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* master device state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct sur40_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct usb_device *usbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct v4l2_device v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct video_device vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct v4l2_pix_format pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct vb2_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct list_head buf_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spinlock_t qlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct sur40_data *bulk_in_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) size_t bulk_in_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 bulk_in_epaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 vsvideo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) char phys[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct sur40_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct vb2_v4l2_buffer vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* forward declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct video_device sur40_video_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct vb2_queue sur40_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void sur40_process_video(struct sur40_state *sur40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int sur40_s_ctrl(struct v4l2_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct v4l2_ctrl_ops sur40_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .s_ctrl = sur40_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Note: an earlier, non-public version of this driver used USB_RECIP_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * here by mistake which is very likely to have corrupted the firmware EEPROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * on two separate SUR40 devices. Thanks to Alan Stern who spotted this bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Should you ever run into a similar problem, the background story to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * incident and instructions on how to fix the corrupted EEPROM are available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * at https://floe.butterbrot.org/matrix/hacking/surface/brick.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* command wrapper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int sur40_command(struct sur40_state *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 command, u16 index, void *buffer, u16 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return usb_control_msg(dev->usbdev, usb_rcvctrlpipe(dev->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x00, index, buffer, size, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* poke a byte in the panel register space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int sur40_poke(struct sur40_state *dev, u8 offset, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 index = 0x96; // 0xae for permanent write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) result = usb_control_msg(dev->usbdev, usb_sndctrlpipe(dev->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SUR40_POKE, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0x32, index, NULL, 0, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) result = usb_control_msg(dev->usbdev, usb_sndctrlpipe(dev->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SUR40_POKE, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x72, offset, NULL, 0, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) result = usb_control_msg(dev->usbdev, usb_sndctrlpipe(dev->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SUR40_POKE, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0xb2, value, NULL, 0, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int sur40_set_preprocessor(struct sur40_state *dev, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 setting_07[2] = { 0x01, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 setting_17[2] = { 0x85, 0x80 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (value > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) result = usb_control_msg(dev->usbdev, usb_sndctrlpipe(dev->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) SUR40_POKE, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x07, setting_07[value], NULL, 0, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) result = usb_control_msg(dev->usbdev, usb_sndctrlpipe(dev->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SUR40_POKE, USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x17, setting_17[value], NULL, 0, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void sur40_set_vsvideo(struct sur40_state *handle, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sur40_poke(handle, 0x1c+i, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) handle->vsvideo = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void sur40_set_irlevel(struct sur40_state *handle, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sur40_poke(handle, 0x08+(2*i), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Initialization routine, called from sur40_open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int sur40_init(struct sur40_state *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) buffer = kmalloc(24, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) result = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* stupidly replay the original MS driver init sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) result = sur40_command(dev, SUR40_GET_VERSION, 0x00, buffer, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) result = sur40_command(dev, SUR40_GET_VERSION, 0x01, buffer, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) result = sur40_command(dev, SUR40_GET_VERSION, 0x02, buffer, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) result = sur40_command(dev, SUR40_SENSOR_CAPS, 0x00, buffer, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) result = sur40_command(dev, SUR40_ACCEL_CAPS, 0x00, buffer, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) result = sur40_command(dev, SUR40_GET_VERSION, 0x03, buffer, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Discard the result buffer - no known data inside except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * some version strings, maybe extract these sometime...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) kfree(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Callback routines from input_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Enable the device, polling will now start. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int sur40_open(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct sur40_state *sur40 = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_dbg(sur40->dev, "open\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return sur40_init(sur40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Disable device, polling has stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void sur40_close(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct sur40_state *sur40 = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_dbg(sur40->dev, "close\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * There is no known way to stop the device, so we simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * stop polling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * This function is called when a whole contact has been processed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * so that it can assign it to a slot and store the data there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void sur40_report_blob(struct sur40_blob *blob, struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int wide, major, minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int bb_size_x, bb_size_y, pos_x, pos_y, ctr_x, ctr_y, slotnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (blob->type != SUR40_TOUCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) slotnum = input_mt_get_slot_by_key(input, blob->blob_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (slotnum < 0 || slotnum >= MAX_CONTACTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) bb_size_x = le16_to_cpu(blob->bb_size_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bb_size_y = le16_to_cpu(blob->bb_size_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pos_x = le16_to_cpu(blob->pos_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pos_y = le16_to_cpu(blob->pos_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ctr_x = le16_to_cpu(blob->ctr_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ctr_y = le16_to_cpu(blob->ctr_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) input_mt_slot(input, slotnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) input_mt_report_slot_state(input, MT_TOOL_FINGER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) wide = (bb_size_x > bb_size_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) major = max(bb_size_x, bb_size_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) minor = min(bb_size_x, bb_size_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) input_report_abs(input, ABS_MT_POSITION_X, pos_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) input_report_abs(input, ABS_MT_POSITION_Y, pos_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) input_report_abs(input, ABS_MT_TOOL_X, ctr_x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) input_report_abs(input, ABS_MT_TOOL_Y, ctr_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* TODO: use a better orientation measure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) input_report_abs(input, ABS_MT_ORIENTATION, wide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) input_report_abs(input, ABS_MT_TOUCH_MAJOR, major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) input_report_abs(input, ABS_MT_TOUCH_MINOR, minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* core function: poll for new input data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void sur40_poll(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct sur40_state *sur40 = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int result, bulk_read, need_blobs, packet_blobs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct sur40_header *header = &sur40->bulk_in_buffer->header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct sur40_blob *inblob = &sur40->bulk_in_buffer->blobs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_dbg(sur40->dev, "poll\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) need_blobs = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* perform a blocking bulk read to get data from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) result = usb_bulk_msg(sur40->usbdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) usb_rcvbulkpipe(sur40->usbdev, sur40->bulk_in_epaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sur40->bulk_in_buffer, sur40->bulk_in_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &bulk_read, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_dbg(sur40->dev, "received %d bytes\n", bulk_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(sur40->dev, "error in usb_bulk_read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) result = bulk_read - sizeof(struct sur40_header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (result % sizeof(struct sur40_blob) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(sur40->dev, "transfer size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* first packet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (need_blobs == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) need_blobs = le16_to_cpu(header->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_dbg(sur40->dev, "need %d blobs\n", need_blobs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* packet_id = le32_to_cpu(header->packet_id); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Sanity check. when video data is also being retrieved, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * packet ID will usually increase in the middle of a series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * instead of at the end. However, the data is still consistent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * so the packet ID is probably just valid for the first packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * in a series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (packet_id != le32_to_cpu(header->packet_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(sur40->dev, "packet ID mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) packet_blobs = result / sizeof(struct sur40_blob);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_dbg(sur40->dev, "received %d blobs\n", packet_blobs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* packets always contain at least 4 blobs, even if empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (packet_blobs > need_blobs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) packet_blobs = need_blobs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) for (i = 0; i < packet_blobs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) need_blobs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_dbg(sur40->dev, "processing blob\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) sur40_report_blob(&(inblob[i]), input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) } while (need_blobs > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) input_mt_sync_frame(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) input_sync(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sur40_process_video(sur40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* deal with video data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void sur40_process_video(struct sur40_state *sur40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct sur40_image_header *img = (void *)(sur40->bulk_in_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct sur40_buffer *new_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct usb_sg_request sgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct sg_table *sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int result, bulk_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!vb2_start_streaming_called(&sur40->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* get a new buffer from the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) spin_lock(&sur40->qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (list_empty(&sur40->buf_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_dbg(sur40->dev, "buffer queue empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) spin_unlock(&sur40->qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) new_buf = list_entry(sur40->buf_list.next, struct sur40_buffer, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) list_del(&new_buf->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) spin_unlock(&sur40->qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_dbg(sur40->dev, "buffer acquired\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* retrieve data via bulk read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) result = usb_bulk_msg(sur40->usbdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) usb_rcvbulkpipe(sur40->usbdev, VIDEO_ENDPOINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sur40->bulk_in_buffer, sur40->bulk_in_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &bulk_read, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(sur40->dev, "error in usb_bulk_read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) goto err_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (bulk_read != sizeof(struct sur40_image_header)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_err(sur40->dev, "received %d bytes (%zd expected)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bulk_read, sizeof(struct sur40_image_header));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto err_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (le32_to_cpu(img->magic) != VIDEO_HEADER_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(sur40->dev, "image magic mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto err_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (le32_to_cpu(img->size) != sur40->pix_fmt.sizeimage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_err(sur40->dev, "image size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) goto err_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_dbg(sur40->dev, "header acquired\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) sgt = vb2_dma_sg_plane_desc(&new_buf->vb.vb2_buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) result = usb_sg_init(&sgr, sur40->usbdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) usb_rcvbulkpipe(sur40->usbdev, VIDEO_ENDPOINT), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) sgt->sgl, sgt->nents, sur40->pix_fmt.sizeimage, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_err(sur40->dev, "error %d in usb_sg_init\n", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) goto err_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) usb_sg_wait(&sgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (sgr.status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_err(sur40->dev, "error %d in usb_sg_wait\n", sgr.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) goto err_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_dbg(sur40->dev, "image acquired\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* return error if streaming was stopped in the meantime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (sur40->sequence == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* mark as finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) new_buf->vb.vb2_buf.timestamp = ktime_get_ns();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) new_buf->vb.sequence = sur40->sequence++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) new_buf->vb.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) vb2_buffer_done(&new_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_dbg(sur40->dev, "buffer marked done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) err_poll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) vb2_buffer_done(&new_buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Initialize input device parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int sur40_input_setup_events(struct input_dev *input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) input_set_abs_params(input_dev, ABS_MT_POSITION_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 0, SENSOR_RES_X, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) input_set_abs_params(input_dev, ABS_MT_POSITION_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 0, SENSOR_RES_Y, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) input_set_abs_params(input_dev, ABS_MT_TOOL_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 0, SENSOR_RES_X, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) input_set_abs_params(input_dev, ABS_MT_TOOL_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 0, SENSOR_RES_Y, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* max value unknown, but major/minor axis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * can never be larger than screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0, SENSOR_RES_X, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) input_set_abs_params(input_dev, ABS_MT_TOUCH_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0, SENSOR_RES_Y, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) input_set_abs_params(input_dev, ABS_MT_ORIENTATION, 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) error = input_mt_init_slots(input_dev, MAX_CONTACTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev_err(input_dev->dev.parent, "failed to set up slots\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Check candidate USB interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int sur40_probe(struct usb_interface *interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct usb_device *usbdev = interface_to_usbdev(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct sur40_state *sur40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct usb_host_interface *iface_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct usb_endpoint_descriptor *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Check if we really have the right interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) iface_desc = interface->cur_altsetting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (iface_desc->desc.bInterfaceClass != 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (iface_desc->desc.bNumEndpoints < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Use endpoint #4 (0x86). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) endpoint = &iface_desc->endpoint[4].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (endpoint->bEndpointAddress != TOUCH_ENDPOINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Allocate memory for our device state and initialize it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) sur40 = kzalloc(sizeof(struct sur40_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!sur40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) input = input_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) goto err_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* initialize locks/lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) INIT_LIST_HEAD(&sur40->buf_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) spin_lock_init(&sur40->qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mutex_init(&sur40->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Set up regular input device structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) input->name = DRIVER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) usb_to_input_id(usbdev, &input->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) usb_make_path(usbdev, sur40->phys, sizeof(sur40->phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) strlcat(sur40->phys, "/input0", sizeof(sur40->phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) input->phys = sur40->phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) input->dev.parent = &interface->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) input->open = sur40_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) input->close = sur40_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) error = sur40_input_setup_events(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) goto err_free_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) input_set_drvdata(input, sur40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) error = input_setup_polling(input, sur40_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_err(&interface->dev, "failed to set up polling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) goto err_free_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) input_set_poll_interval(input, POLL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) sur40->usbdev = usbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) sur40->dev = &interface->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) sur40->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* use the bulk-in endpoint tested above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) sur40->bulk_in_size = usb_endpoint_maxp(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) sur40->bulk_in_epaddr = endpoint->bEndpointAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) sur40->bulk_in_buffer = kmalloc(sur40->bulk_in_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!sur40->bulk_in_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_err(&interface->dev, "Unable to allocate input buffer.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto err_free_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* register the polled input device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) error = input_register_device(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_err(&interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "Unable to register polled input device.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) goto err_free_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* register the video master device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) snprintf(sur40->v4l2.name, sizeof(sur40->v4l2.name), "%s", DRIVER_LONG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) error = v4l2_device_register(sur40->dev, &sur40->v4l2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_err(&interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "Unable to register video master device.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) goto err_unreg_v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* initialize the lock and subdevice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) sur40->queue = sur40_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) sur40->queue.drv_priv = sur40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) sur40->queue.lock = &sur40->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) sur40->queue.dev = sur40->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* initialize the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) error = vb2_queue_init(&sur40->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) goto err_unreg_v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) sur40->pix_fmt = sur40_pix_format[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) sur40->vdev = sur40_video_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) sur40->vdev.v4l2_dev = &sur40->v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) sur40->vdev.lock = &sur40->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) sur40->vdev.queue = &sur40->queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) video_set_drvdata(&sur40->vdev, sur40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* initialize the control handler for 4 controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) v4l2_ctrl_handler_init(&sur40->hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) sur40->v4l2.ctrl_handler = &sur40->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) sur40->vsvideo = (SUR40_CONTRAST_DEF << 4) | SUR40_GAIN_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) v4l2_ctrl_new_std(&sur40->hdl, &sur40_ctrl_ops, V4L2_CID_BRIGHTNESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) SUR40_BRIGHTNESS_MIN, SUR40_BRIGHTNESS_MAX, 1, clamp(brightness,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) (uint)SUR40_BRIGHTNESS_MIN, (uint)SUR40_BRIGHTNESS_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) v4l2_ctrl_new_std(&sur40->hdl, &sur40_ctrl_ops, V4L2_CID_CONTRAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) SUR40_CONTRAST_MIN, SUR40_CONTRAST_MAX, 1, clamp(contrast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) (uint)SUR40_CONTRAST_MIN, (uint)SUR40_CONTRAST_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) v4l2_ctrl_new_std(&sur40->hdl, &sur40_ctrl_ops, V4L2_CID_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) SUR40_GAIN_MIN, SUR40_GAIN_MAX, 1, clamp(gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) (uint)SUR40_GAIN_MIN, (uint)SUR40_GAIN_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) v4l2_ctrl_new_std(&sur40->hdl, &sur40_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) V4L2_CID_BACKLIGHT_COMPENSATION, SUR40_BACKLIGHT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) SUR40_BACKLIGHT_MAX, 1, SUR40_BACKLIGHT_DEF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) v4l2_ctrl_handler_setup(&sur40->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (sur40->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(&interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "Unable to register video controls.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) v4l2_ctrl_handler_free(&sur40->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) error = sur40->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) goto err_unreg_v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) error = video_register_device(&sur40->vdev, VFL_TYPE_TOUCH, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_err(&interface->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "Unable to register video subdevice.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) goto err_unreg_video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* we can register the device now, as it is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) usb_set_intfdata(interface, sur40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dev_dbg(&interface->dev, "%s is now attached\n", DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) err_unreg_video:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) video_unregister_device(&sur40->vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) err_unreg_v4l2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) v4l2_device_unregister(&sur40->v4l2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) err_free_buffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) kfree(sur40->bulk_in_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) err_free_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) input_free_device(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) err_free_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) kfree(sur40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Unregister device & clean up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static void sur40_disconnect(struct usb_interface *interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct sur40_state *sur40 = usb_get_intfdata(interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) v4l2_ctrl_handler_free(&sur40->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) video_unregister_device(&sur40->vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) v4l2_device_unregister(&sur40->v4l2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) input_unregister_device(sur40->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) kfree(sur40->bulk_in_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) kfree(sur40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) usb_set_intfdata(interface, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_dbg(&interface->dev, "%s is now disconnected\n", DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * Setup the constraints of the queue: besides setting the number of planes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * per buffer and the size and allocation context of each plane, it also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * checks if sufficient buffers have been allocated. Usually 3 is a good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * minimum number: many DMA engines need a minimum of 2 buffers in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * queue and you need to have another available for userspace processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int sur40_queue_setup(struct vb2_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) unsigned int *nbuffers, unsigned int *nplanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) unsigned int sizes[], struct device *alloc_devs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct sur40_state *sur40 = vb2_get_drv_priv(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (q->num_buffers + *nbuffers < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) *nbuffers = 3 - q->num_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (*nplanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return sizes[0] < sur40->pix_fmt.sizeimage ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) *nplanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) sizes[0] = sur40->pix_fmt.sizeimage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * Prepare the buffer for queueing to the DMA engine: check and set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * payload size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int sur40_buffer_prepare(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct sur40_state *sur40 = vb2_get_drv_priv(vb->vb2_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned long size = sur40->pix_fmt.sizeimage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (vb2_plane_size(vb, 0) < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_err(&sur40->usbdev->dev, "buffer too small (%lu < %lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) vb2_plane_size(vb, 0), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) vb2_set_plane_payload(vb, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * Queue this buffer to the DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static void sur40_buffer_queue(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct sur40_state *sur40 = vb2_get_drv_priv(vb->vb2_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct sur40_buffer *buf = (struct sur40_buffer *)vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) spin_lock(&sur40->qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) list_add_tail(&buf->list, &sur40->buf_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) spin_unlock(&sur40->qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static void return_all_buffers(struct sur40_state *sur40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) enum vb2_buffer_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct sur40_buffer *buf, *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) spin_lock(&sur40->qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) list_for_each_entry_safe(buf, node, &sur40->buf_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) vb2_buffer_done(&buf->vb.vb2_buf, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) list_del(&buf->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) spin_unlock(&sur40->qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * Start streaming. First check if the minimum number of buffers have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * queued. If not, then return -ENOBUFS and the vb2 framework will call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * this function again the next time a buffer has been queued until enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * buffers are available to actually start the DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int sur40_start_streaming(struct vb2_queue *vq, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct sur40_state *sur40 = vb2_get_drv_priv(vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) sur40->sequence = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * Stop the DMA engine. Any remaining buffers in the DMA queue are dequeued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * and passed on to the vb2 framework marked as STATE_ERROR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static void sur40_stop_streaming(struct vb2_queue *vq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct sur40_state *sur40 = vb2_get_drv_priv(vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) vb2_wait_for_all_buffers(vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) sur40->sequence = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Release all active buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return_all_buffers(sur40, VB2_BUF_STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* V4L ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int sur40_vidioc_querycap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct v4l2_capability *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct sur40_state *sur40 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) strlcpy(cap->driver, DRIVER_SHORT, sizeof(cap->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) strlcpy(cap->card, DRIVER_LONG, sizeof(cap->card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) usb_make_path(sur40->usbdev, cap->bus_info, sizeof(cap->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int sur40_vidioc_enum_input(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct v4l2_input *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (i->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) i->type = V4L2_INPUT_TYPE_TOUCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) i->std = V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) strlcpy(i->name, "In-Cell Sensor", sizeof(i->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) i->capabilities = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int sur40_vidioc_s_input(struct file *file, void *priv, unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return (i == 0) ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int sur40_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) *i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static int sur40_vidioc_try_fmt(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) switch (f->fmt.pix.pixelformat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case V4L2_PIX_FMT_GREY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) f->fmt.pix = sur40_pix_format[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) f->fmt.pix = sur40_pix_format[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int sur40_vidioc_s_fmt(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct sur40_state *sur40 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) switch (f->fmt.pix.pixelformat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case V4L2_PIX_FMT_GREY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) sur40->pix_fmt = sur40_pix_format[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) sur40->pix_fmt = sur40_pix_format[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) f->fmt.pix = sur40->pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static int sur40_vidioc_g_fmt(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct sur40_state *sur40 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) f->fmt.pix = sur40->pix_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static int sur40_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct sur40_state *sur40 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct sur40_state, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u8 value = sur40->vsvideo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) sur40_set_irlevel(sur40, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) value = (value & 0x0f) | (ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sur40_set_vsvideo(sur40, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) value = (value & 0xf0) | (ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) sur40_set_vsvideo(sur40, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) case V4L2_CID_BACKLIGHT_COMPENSATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) sur40_set_preprocessor(sur40, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int sur40_ioctl_parm(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct v4l2_streamparm *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (p->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) p->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) p->parm.capture.timeperframe.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) p->parm.capture.timeperframe.denominator = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) p->parm.capture.readbuffers = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int sur40_vidioc_enum_fmt(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct v4l2_fmtdesc *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (f->index >= ARRAY_SIZE(sur40_pix_format))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) f->pixelformat = sur40_pix_format[f->index].pixelformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) f->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static int sur40_vidioc_enum_framesizes(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct v4l2_frmsizeenum *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct sur40_state *sur40 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if ((f->index != 0) || ((f->pixel_format != V4L2_TCH_FMT_TU08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) && (f->pixel_format != V4L2_PIX_FMT_GREY)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) f->type = V4L2_FRMSIZE_TYPE_DISCRETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) f->discrete.width = sur40->pix_fmt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) f->discrete.height = sur40->pix_fmt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static int sur40_vidioc_enum_frameintervals(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct v4l2_frmivalenum *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct sur40_state *sur40 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if ((f->index > 0) || ((f->pixel_format != V4L2_TCH_FMT_TU08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) && (f->pixel_format != V4L2_PIX_FMT_GREY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) || (f->width != sur40->pix_fmt.width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) || (f->height != sur40->pix_fmt.height))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) f->type = V4L2_FRMIVAL_TYPE_DISCRETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) f->discrete.denominator = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) f->discrete.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const struct usb_device_id sur40_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) { USB_DEVICE(ID_MICROSOFT, ID_SUR40) }, /* Samsung SUR40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) { } /* terminating null entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) MODULE_DEVICE_TABLE(usb, sur40_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* V4L2 structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const struct vb2_ops sur40_queue_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .queue_setup = sur40_queue_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .buf_prepare = sur40_buffer_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .buf_queue = sur40_buffer_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .start_streaming = sur40_start_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .stop_streaming = sur40_stop_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .wait_prepare = vb2_ops_wait_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .wait_finish = vb2_ops_wait_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const struct vb2_queue sur40_queue = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * VB2_USERPTR in currently not enabled: passing a user pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * dma-sg will result in segment sizes that are not a multiple of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * 512 bytes, which is required by the host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .buf_struct_size = sizeof(struct sur40_buffer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .ops = &sur40_queue_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .mem_ops = &vb2_dma_sg_memops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .min_buffers_needed = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const struct v4l2_file_operations sur40_video_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .open = v4l2_fh_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .release = vb2_fop_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .unlocked_ioctl = video_ioctl2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .read = vb2_fop_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .mmap = vb2_fop_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .poll = vb2_fop_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static const struct v4l2_ioctl_ops sur40_video_ioctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .vidioc_querycap = sur40_vidioc_querycap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .vidioc_enum_fmt_vid_cap = sur40_vidioc_enum_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .vidioc_try_fmt_vid_cap = sur40_vidioc_try_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .vidioc_s_fmt_vid_cap = sur40_vidioc_s_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .vidioc_g_fmt_vid_cap = sur40_vidioc_g_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .vidioc_enum_framesizes = sur40_vidioc_enum_framesizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .vidioc_enum_frameintervals = sur40_vidioc_enum_frameintervals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .vidioc_g_parm = sur40_ioctl_parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .vidioc_s_parm = sur40_ioctl_parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .vidioc_enum_input = sur40_vidioc_enum_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .vidioc_g_input = sur40_vidioc_g_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .vidioc_s_input = sur40_vidioc_s_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .vidioc_reqbufs = vb2_ioctl_reqbufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .vidioc_create_bufs = vb2_ioctl_create_bufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .vidioc_querybuf = vb2_ioctl_querybuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .vidioc_qbuf = vb2_ioctl_qbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .vidioc_dqbuf = vb2_ioctl_dqbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .vidioc_expbuf = vb2_ioctl_expbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .vidioc_streamon = vb2_ioctl_streamon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .vidioc_streamoff = vb2_ioctl_streamoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static const struct video_device sur40_video_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .name = DRIVER_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .fops = &sur40_video_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .ioctl_ops = &sur40_video_ioctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .release = video_device_release_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TOUCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) V4L2_CAP_READWRITE | V4L2_CAP_STREAMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* USB-specific object needed to register this driver with the USB subsystem. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static struct usb_driver sur40_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .name = DRIVER_SHORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .probe = sur40_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .disconnect = sur40_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .id_table = sur40_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) module_usb_driver(sur40_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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