^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * LPC32xx built-in touchscreen driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Touchscreen controller register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPC32XX_TSC_STAT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPC32XX_TSC_SEL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPC32XX_TSC_CON 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPC32XX_TSC_FIFO 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPC32XX_TSC_DTR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPC32XX_TSC_RTR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPC32XX_TSC_UTR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPC32XX_TSC_TTR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPC32XX_TSC_DXP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC32XX_TSC_MIN_X 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC32XX_TSC_MAX_X 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC32XX_TSC_MIN_Y 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC32XX_TSC_MAX_Y 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC32XX_TSC_AUX_UTR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC32XX_TSC_AUX_MIN 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC32XX_TSC_AUX_MAX 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC32XX_TSC_STAT_FIFO_OVRRN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPC32XX_TSC_STAT_FIFO_EMPTY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC32XX_TSC_SEL_DEFVAL 0x0284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 (0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPC32XX_TSC_ADCCON_POWER_UP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPC32XX_TSC_ADCCON_AUTO_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(x) (((x) & 0x03FF0000) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(y) ((y) & 0x000003FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LPC32XX_TSC_MIN_XY_VAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPC32XX_TSC_MAX_XY_VAL 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MOD_NAME "ts-lpc32xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define tsc_readl(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __raw_readl((dev)->tsc_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define tsc_writel(dev, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __raw_writel((val), (dev)->tsc_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct lpc32xx_tsc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct input_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *tsc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) LPC32XX_TSC_STAT_FIFO_EMPTY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tsc_readl(tsc, LPC32XX_TSC_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static irqreturn_t lpc32xx_ts_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 tmp, rv[4], xs[4], ys[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct lpc32xx_tsc *tsc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct input_dev *input = tsc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tmp = tsc_readl(tsc, LPC32XX_TSC_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (tmp & LPC32XX_TSC_STAT_FIFO_OVRRN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* FIFO overflow - throw away samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) lpc32xx_fifo_clear(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Gather and normalize 4 samples. Pen-up events may have less
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * than 4 samples, but its ok to pop 4 and let the last sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * pen status check drop the samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) while (idx < 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) !(tsc_readl(tsc, LPC32XX_TSC_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) LPC32XX_TSC_STAT_FIFO_EMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tmp = tsc_readl(tsc, LPC32XX_TSC_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) xs[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ys[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rv[idx] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Data is only valid if pen is still down in last sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!(rv[3] & LPC32XX_TSC_FIFO_TS_P_LEVEL) && idx == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Use average of 2nd and 3rd sample for position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) input_report_abs(input, ABS_X, (xs[1] + xs[2]) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) input_report_abs(input, ABS_Y, (ys[1] + ys[2]) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) input_report_key(input, BTN_TOUCH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) input_report_key(input, BTN_TOUCH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) input_sync(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void lpc32xx_stop_tsc(struct lpc32xx_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Disable auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tsc_writel(tsc, LPC32XX_TSC_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tsc_readl(tsc, LPC32XX_TSC_CON) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ~LPC32XX_TSC_ADCCON_AUTO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clk_disable_unprepare(tsc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int lpc32xx_setup_tsc(struct lpc32xx_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) err = clk_prepare_enable(tsc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tmp = tsc_readl(tsc, LPC32XX_TSC_CON) & ~LPC32XX_TSC_ADCCON_POWER_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Set the TSC FIFO depth to 4 samples @ 10-bits per sample (max) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tmp = LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tsc_writel(tsc, LPC32XX_TSC_CON, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* These values are all preset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tsc_writel(tsc, LPC32XX_TSC_SEL, LPC32XX_TSC_SEL_DEFVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tsc_writel(tsc, LPC32XX_TSC_MIN_X, LPC32XX_TSC_MIN_XY_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tsc_writel(tsc, LPC32XX_TSC_MAX_X, LPC32XX_TSC_MAX_XY_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tsc_writel(tsc, LPC32XX_TSC_MIN_Y, LPC32XX_TSC_MIN_XY_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tsc_writel(tsc, LPC32XX_TSC_MAX_Y, LPC32XX_TSC_MAX_XY_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Aux support is not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tsc_writel(tsc, LPC32XX_TSC_AUX_UTR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tsc_writel(tsc, LPC32XX_TSC_AUX_MIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tsc_writel(tsc, LPC32XX_TSC_AUX_MAX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Set sample rate to about 240Hz per X/Y pair. A single measurement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * consists of 4 pairs which gives about a 60Hz sample rate based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * a stable 32768Hz clock source. Values are in clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Rate is (32768 / (RTR + XCONV + RTR + YCONV + DXP + TTR + UTR) / 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) tsc_writel(tsc, LPC32XX_TSC_RTR, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tsc_writel(tsc, LPC32XX_TSC_DTR, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tsc_writel(tsc, LPC32XX_TSC_TTR, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tsc_writel(tsc, LPC32XX_TSC_DXP, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tsc_writel(tsc, LPC32XX_TSC_UTR, 88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) lpc32xx_fifo_clear(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Enable automatic ts event capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tsc_writel(tsc, LPC32XX_TSC_CON, tmp | LPC32XX_TSC_ADCCON_AUTO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int lpc32xx_ts_open(struct input_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return lpc32xx_setup_tsc(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void lpc32xx_ts_close(struct input_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) lpc32xx_stop_tsc(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int lpc32xx_ts_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct lpc32xx_tsc *tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(&pdev->dev, "Can't get memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tsc = kzalloc(sizeof(*tsc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) input = input_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!tsc || !input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(&pdev->dev, "failed allocating memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tsc->dev = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tsc->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!request_mem_region(res->start, size, pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(&pdev->dev, "TSC registers are not free\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) error = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tsc->tsc_base = ioremap(res->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!tsc->tsc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(&pdev->dev, "Can't map memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) goto err_release_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tsc->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (IS_ERR(tsc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_err(&pdev->dev, "failed getting clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) error = PTR_ERR(tsc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) input->name = MOD_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) input->phys = "lpc32xx/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) input->id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) input->id.vendor = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) input->id.product = 0x0002;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) input->id.version = 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) input->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) input->open = lpc32xx_ts_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) input->close = lpc32xx_ts_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) input_set_abs_params(input, ABS_X, LPC32XX_TSC_MIN_XY_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) LPC32XX_TSC_MAX_XY_VAL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) input_set_abs_params(input, ABS_Y, LPC32XX_TSC_MIN_XY_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) LPC32XX_TSC_MAX_XY_VAL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) input_set_drvdata(input, tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) error = request_irq(tsc->irq, lpc32xx_ts_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0, pdev->name, tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(&pdev->dev, "failed requesting interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto err_put_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) error = input_register_device(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(&pdev->dev, "failed registering input device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) platform_set_drvdata(pdev, tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) free_irq(tsc->irq, tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err_put_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clk_put(tsc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) iounmap(tsc->tsc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) err_release_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) release_mem_region(res->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) err_free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) input_free_device(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) kfree(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int lpc32xx_ts_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct lpc32xx_tsc *tsc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) free_irq(tsc->irq, tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) input_unregister_device(tsc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) clk_put(tsc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) iounmap(tsc->tsc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) kfree(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int lpc32xx_ts_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct input_dev *input = tsc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Suspend and resume can be called when the device hasn't been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * enabled. If there are no users that have the device open, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * avoid calling the TSC stop and start functions as the TSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * isn't yet clocked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mutex_lock(&input->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (input->users) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enable_irq_wake(tsc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) lpc32xx_stop_tsc(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mutex_unlock(&input->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int lpc32xx_ts_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct input_dev *input = tsc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mutex_lock(&input->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (input->users) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) disable_irq_wake(tsc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) lpc32xx_setup_tsc(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mutex_unlock(&input->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct dev_pm_ops lpc32xx_ts_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .suspend = lpc32xx_ts_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .resume = lpc32xx_ts_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define LPC32XX_TS_PM_OPS (&lpc32xx_ts_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define LPC32XX_TS_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct of_device_id lpc32xx_tsc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { .compatible = "nxp,lpc3220-tsc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_DEVICE_TABLE(of, lpc32xx_tsc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct platform_driver lpc32xx_ts_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .probe = lpc32xx_ts_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .remove = lpc32xx_ts_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = MOD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pm = LPC32XX_TS_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .of_match_table = of_match_ptr(lpc32xx_tsc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) module_platform_driver(lpc32xx_ts_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MODULE_DESCRIPTION("LPC32XX TSC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MODULE_ALIAS("platform:lpc32xx_ts");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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