^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Freescale i.MX6UL touchscreen controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* ADC configuration registers field define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADC_AIEN (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADC_CONV_DISABLE 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADC_AVGE (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADC_CAL (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADC_CALF 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADC_12BIT_MODE (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADC_CONV_MODE_MASK (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADC_IPG_CLK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADC_INPUT_CLK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADC_CLK_DIV_8 (0x03 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADC_CLK_DIV_MASK (0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADC_SHORT_SAMPLE_MODE (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ADC_SAMPLE_MODE_MASK (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADC_HARDWARE_TRIGGER (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADC_AVGS_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADC_AVGS_MASK (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SELECT_CHANNEL_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SELECT_CHANNEL_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DISABLE_CONVERSION_INT (0x0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* ADC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_ADC_HC0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_ADC_HC1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_ADC_HC2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_ADC_HC3 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_ADC_HC4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_ADC_HS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_ADC_R0 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_ADC_CFG 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_ADC_GC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_ADC_GS 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADC_TIMEOUT msecs_to_jiffies(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* TSC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_TSC_BASIC_SETING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_TSC_PRE_CHARGE_TIME 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_TSC_FLOW_CONTROL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_TSC_MEASURE_VALUE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_TSC_INT_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_TSC_INT_SIG_EN 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_TSC_INT_STATUS 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_TSC_DEBUG_MODE 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_TSC_DEBUG_MODE2 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* TSC configuration registers field define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DETECT_4_WIRE_MODE (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AUTO_MEASURE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MEASURE_SIGNAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DETECT_SIGNAL (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VALID_SIGNAL (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MEASURE_INT_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MEASURE_SIG_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VALID_SIG_EN (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DE_GLITCH_2 (0x2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define START_SENSE (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TSC_DISABLE (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DETECT_MODE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct imx6ul_tsc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *tsc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *adc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *tsc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk *adc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct gpio_desc *xnur_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 measure_delay_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 pre_charge_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool average_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 average_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * TSC module need ADC to get the measure value. So
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * before config TSC, we should initialize ADC module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int imx6ul_adc_init(struct imx6ul_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 adc_hc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 adc_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 adc_gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 adc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reinit_completion(&tsc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) adc_cfg &= ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) adc_cfg |= ADC_12BIT_MODE | ADC_IPG_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) adc_cfg |= ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (tsc->average_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) adc_cfg &= ~ADC_AVGS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) adc_cfg &= ~ADC_HARDWARE_TRIGGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* enable calibration interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) adc_hc |= ADC_AIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) adc_hc |= ADC_CONV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writel(adc_hc, tsc->adc_regs + REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* start ADC calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) adc_gc = readl(tsc->adc_regs + REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) adc_gc |= ADC_CAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (tsc->average_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) adc_gc |= ADC_AVGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(adc_gc, tsc->adc_regs + REG_ADC_GC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) timeout = wait_for_completion_timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (&tsc->completion, ADC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(tsc->dev, "Timeout for adc calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) adc_gs = readl(tsc->adc_regs + REG_ADC_GS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (adc_gs & ADC_CALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(tsc->dev, "ADC calibration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* TSC need the ADC work in hardware trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) adc_cfg |= ADC_HARDWARE_TRIGGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * This is a TSC workaround. Currently TSC misconnect two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * ADC channels, this function remap channel configure for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * hardware trigger.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) adc_hc0 = DISABLE_CONVERSION_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) adc_hc1 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) adc_hc2 = DISABLE_CONVERSION_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) adc_hc3 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) adc_hc4 = DISABLE_CONVERSION_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * TSC setting, confige the pre-charge time and measure delay time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * different touch screen may need different pre-charge time and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * measure delay time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void imx6ul_tsc_set(struct imx6ul_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 basic_setting = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) basic_setting |= tsc->measure_delay_time << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) basic_setting |= DETECT_4_WIRE_MODE | AUTO_MEASURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel(MEASURE_SIG_EN | VALID_SIG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tsc->tsc_regs + REG_TSC_INT_SIG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* start sense detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) start |= START_SENSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) start &= ~TSC_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int imx6ul_tsc_init(struct imx6ul_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) err = imx6ul_adc_init(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) imx6ul_tsc_channel_config(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) imx6ul_tsc_set(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void imx6ul_tsc_disable(struct imx6ul_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 tsc_flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 adc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* TSC controller enters to idle status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tsc_flow = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) tsc_flow |= TSC_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(tsc_flow, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* ADC controller enters to stop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) adc_cfg = readl(tsc->adc_regs + REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) adc_cfg |= ADC_CONV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel(adc_cfg, tsc->adc_regs + REG_ADC_HC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Delay some time (max 2ms), wait the pre-charge done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long timeout = jiffies + msecs_to_jiffies(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 state_machine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 debug_mode2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) usleep_range(200, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) debug_mode2 = readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) state_machine = (debug_mode2 >> 20) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } while (state_machine != DETECT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) usleep_range(200, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static irqreturn_t tsc_irq_fn(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct imx6ul_tsc *tsc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) status = readl(tsc->tsc_regs + REG_TSC_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* write 1 to clear the bit measure-signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel(MEASURE_SIGNAL | DETECT_SIGNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tsc->tsc_regs + REG_TSC_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* It's a HW self-clean bit. Set this bit and start sense detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) start |= START_SENSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (status & MEASURE_SIGNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) value = readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) x = (value >> 16) & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) y = value & 0x0fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * In detect mode, we can get the xnur gpio value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * otherwise assume contact is stiull active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!tsc_wait_detect_mode(tsc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) gpiod_get_value_cansleep(tsc->xnur_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) input_report_key(tsc->input, BTN_TOUCH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) input_report_abs(tsc->input, ABS_X, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) input_report_abs(tsc->input, ABS_Y, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) input_report_key(tsc->input, BTN_TOUCH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) input_sync(tsc->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static irqreturn_t adc_irq_fn(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct imx6ul_tsc *tsc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 coco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) coco = readl(tsc->adc_regs + REG_ADC_HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (coco & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) value = readl(tsc->adc_regs + REG_ADC_R0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) complete(&tsc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int imx6ul_tsc_start(struct imx6ul_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) err = clk_prepare_enable(tsc->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(tsc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "Could not prepare or enable the adc clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) err = clk_prepare_enable(tsc->tsc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(tsc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "Could not prepare or enable the tsc clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto disable_adc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err = imx6ul_tsc_init(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto disable_tsc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) disable_tsc_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) clk_disable_unprepare(tsc->tsc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) disable_adc_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) clk_disable_unprepare(tsc->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void imx6ul_tsc_stop(struct imx6ul_tsc *tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) imx6ul_tsc_disable(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) clk_disable_unprepare(tsc->tsc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) clk_disable_unprepare(tsc->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int imx6ul_tsc_open(struct input_dev *input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return imx6ul_tsc_start(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static void imx6ul_tsc_close(struct input_dev *input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) imx6ul_tsc_stop(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int imx6ul_tsc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct imx6ul_tsc *tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct input_dev *input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int tsc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int adc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 average_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) tsc = devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!tsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) input_dev = devm_input_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) input_dev->name = "iMX6UL Touchscreen Controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) input_dev->id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) input_dev->open = imx6ul_tsc_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) input_dev->close = imx6ul_tsc_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) input_set_abs_params(input_dev, ABS_X, 0, 0xFFF, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) input_set_abs_params(input_dev, ABS_Y, 0, 0xFFF, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) input_set_drvdata(input_dev, tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) tsc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tsc->input = input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) init_completion(&tsc->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tsc->xnur_gpio = devm_gpiod_get(&pdev->dev, "xnur", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (IS_ERR(tsc->xnur_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) err = PTR_ERR(tsc->xnur_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "failed to request GPIO tsc_X- (xnur): %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tsc->tsc_regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (IS_ERR(tsc->tsc_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) err = PTR_ERR(tsc->tsc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(&pdev->dev, "failed to remap tsc memory: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tsc->adc_regs = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (IS_ERR(tsc->adc_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) err = PTR_ERR(tsc->adc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&pdev->dev, "failed to remap adc memory: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tsc->tsc_clk = devm_clk_get(&pdev->dev, "tsc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (IS_ERR(tsc->tsc_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err = PTR_ERR(tsc->tsc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(&pdev->dev, "failed getting tsc clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tsc->adc_clk = devm_clk_get(&pdev->dev, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (IS_ERR(tsc->adc_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) err = PTR_ERR(tsc->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(&pdev->dev, "failed getting adc clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tsc_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (tsc_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return tsc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) adc_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (adc_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return adc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) err = devm_request_threaded_irq(tsc->dev, tsc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) NULL, tsc_irq_fn, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_name(&pdev->dev), tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "failed requesting tsc irq %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) tsc_irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err = devm_request_irq(tsc->dev, adc_irq, adc_irq_fn, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_name(&pdev->dev), tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "failed requesting adc irq %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) adc_irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) err = of_property_read_u32(np, "measure-delay-time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &tsc->measure_delay_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tsc->measure_delay_time = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) err = of_property_read_u32(np, "pre-charge-time",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &tsc->pre_charge_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) tsc->pre_charge_time = 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) err = of_property_read_u32(np, "touchscreen-average-samples",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &average_samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) average_samples = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) switch (average_samples) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) tsc->average_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tsc->average_select = 0; /* value unused; initialize anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tsc->average_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tsc->average_select = ilog2(average_samples) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "touchscreen-average-samples (%u) must be 1, 4, 8, 16 or 32\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) average_samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) err = input_register_device(tsc->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "failed to register input device: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) platform_set_drvdata(pdev, tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int __maybe_unused imx6ul_tsc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct input_dev *input_dev = tsc->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mutex_lock(&input_dev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (input_dev->users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) imx6ul_tsc_stop(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mutex_unlock(&input_dev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int __maybe_unused imx6ul_tsc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct input_dev *input_dev = tsc->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mutex_lock(&input_dev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (input_dev->users)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) retval = imx6ul_tsc_start(tsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_unlock(&input_dev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static SIMPLE_DEV_PM_OPS(imx6ul_tsc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) imx6ul_tsc_suspend, imx6ul_tsc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct of_device_id imx6ul_tsc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { .compatible = "fsl,imx6ul-tsc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MODULE_DEVICE_TABLE(of, imx6ul_tsc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct platform_driver imx6ul_tsc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .name = "imx6ul-tsc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .of_match_table = imx6ul_tsc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .pm = &imx6ul_tsc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .probe = imx6ul_tsc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) module_platform_driver(imx6ul_tsc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MODULE_DESCRIPTION("Freescale i.MX6UL Touchscreen controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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