Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *	Driver for Allwinner A10 PS2 host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	Author: Vishnu Patekar <vishnupatekar0510@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *		Aaron.maoye <leafy.myeh@newbietech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/serio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DRIVER_NAME		"sun4i-ps2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* register offset definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PS2_REG_GCTL		0x00	/* PS2 Module Global Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PS2_REG_DATA		0x04	/* PS2 Module Data Reg		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PS2_REG_LCTL		0x08	/* PS2 Module Line Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PS2_REG_LSTS		0x0C	/* PS2 Module Line Status Reg	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PS2_REG_FCTL		0x10	/* PS2 Module FIFO Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PS2_REG_FSTS		0x14	/* PS2 Module FIFO Status Reg	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PS2_REG_CLKDR		0x18	/* PS2 Module Clock Divider Reg*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*  PS2 GLOBAL CONTROL REGISTER PS2_GCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PS2_GCTL_INTFLAG	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PS2_GCTL_INTEN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PS2_GCTL_RESET		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PS2_GCTL_MASTER		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PS2_GCTL_BUSEN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* PS2 LINE CONTROL REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PS2_LCTL_NOACK		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PS2_LCTL_TXDTOEN	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PS2_LCTL_STOPERREN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PS2_LCTL_ACKERREN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PS2_LCTL_PARERREN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PS2_LCTL_RXDTOEN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* PS2 LINE STATUS REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PS2_LSTS_TXTDO		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PS2_LSTS_STOPERR	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PS2_LSTS_ACKERR		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PS2_LSTS_PARERR		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PS2_LSTS_RXTDO		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PS2_LINE_ERROR_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	(PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	PS2_LSTS_PARERR | PS2_LSTS_RXTDO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* PS2 FIFO CONTROL REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PS2_FCTL_TXRST		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PS2_FCTL_RXRST		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PS2_FCTL_TXUFIEN	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PS2_FCTL_TXOFIEN	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PS2_FCTL_TXRDYIEN	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PS2_FCTL_RXUFIEN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PS2_FCTL_RXOFIEN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PS2_FCTL_RXRDYIEN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* PS2 FIFO STATUS REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PS2_FSTS_TXUF		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PS2_FSTS_TXOF		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PS2_FSTS_TXRDY		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PS2_FSTS_RXUF		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PS2_FSTS_RXOF		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PS2_FSTS_RXRDY		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PS2_FIFO_ERROR_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	(PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_RXUF | PS2_FSTS_RXOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PS2_SAMPLE_CLK		1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PS2_SCLK		125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) struct sun4i_ps2data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct serio *serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* IO mapping base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	void __iomem	*reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* clock management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct clk	*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	spinlock_t	lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int		irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static irqreturn_t sun4i_ps2_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct sun4i_ps2data *drvdata = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned char byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned int rxflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	spin_lock(&drvdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* Get the PS/2 interrupts and clear them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	intr_status  = readl(drvdata->reg_base + PS2_REG_LSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	fifo_status  = readl(drvdata->reg_base + PS2_REG_FSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* Check line status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (intr_status & PS2_LINE_ERROR_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		rxflags = (intr_status & PS2_LINE_ERROR_BIT) ? SERIO_FRAME : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_PARITY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		rxflags |= (intr_status & PS2_LSTS_PARERR) ? SERIO_TIMEOUT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		rval = PS2_LSTS_TXTDO | PS2_LSTS_STOPERR | PS2_LSTS_ACKERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			PS2_LSTS_PARERR | PS2_LSTS_RXTDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		writel(rval, drvdata->reg_base + PS2_REG_LSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* Check FIFO status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (fifo_status & PS2_FIFO_ERROR_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		rval = PS2_FSTS_TXUF | PS2_FSTS_TXOF | PS2_FSTS_TXRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			PS2_FSTS_RXUF | PS2_FSTS_RXOF | PS2_FSTS_RXRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		writel(rval, drvdata->reg_base + PS2_REG_FSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	rval = (fifo_status >> 16) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	while (rval--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		serio_interrupt(drvdata->serio, byte, rxflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	writel(intr_status, drvdata->reg_base + PS2_REG_LSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	spin_unlock(&drvdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int sun4i_ps2_open(struct serio *serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct sun4i_ps2data *drvdata = serio->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32 src_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u32 clk_scdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u32 clk_pcdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* Set line control and enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	rval = PS2_LCTL_STOPERREN | PS2_LCTL_ACKERREN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		| PS2_LCTL_PARERREN | PS2_LCTL_RXDTOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	writel(rval, drvdata->reg_base + PS2_REG_LCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Reset FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	rval = PS2_FCTL_TXRST | PS2_FCTL_RXRST | PS2_FCTL_TXUFIEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		| PS2_FCTL_TXOFIEN | PS2_FCTL_RXUFIEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		| PS2_FCTL_RXOFIEN | PS2_FCTL_RXRDYIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	writel(rval, drvdata->reg_base + PS2_REG_FCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	src_clk = clk_get_rate(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* Set clock divider register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	clk_scdf = src_clk / PS2_SAMPLE_CLK - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	clk_pcdf = PS2_SAMPLE_CLK / PS2_SCLK - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	rval = (clk_scdf << 8) | clk_pcdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	writel(rval, drvdata->reg_base + PS2_REG_CLKDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* Set global control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	rval = PS2_GCTL_RESET | PS2_GCTL_INTEN | PS2_GCTL_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		| PS2_GCTL_BUSEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	spin_lock_irqsave(&drvdata->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	writel(rval, drvdata->reg_base + PS2_REG_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	spin_unlock_irqrestore(&drvdata->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void sun4i_ps2_close(struct serio *serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct sun4i_ps2data *drvdata = serio->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Shut off the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	rval = readl(drvdata->reg_base + PS2_REG_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	synchronize_irq(drvdata->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int sun4i_ps2_write(struct serio *serio, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	unsigned long expire = jiffies + msecs_to_jiffies(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct sun4i_ps2data *drvdata = serio->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		if (readl(drvdata->reg_base + PS2_REG_FSTS) & PS2_FSTS_TXRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			writel(val, drvdata->reg_base + PS2_REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	} while (time_before(jiffies, expire));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return SERIO_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int sun4i_ps2_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct resource *res; /* IO mem resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct sun4i_ps2data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct serio *serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	drvdata = kzalloc(sizeof(struct sun4i_ps2data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (!drvdata || !serio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	spin_lock_init(&drvdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		dev_err(dev, "failed to locate registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		error = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	drvdata->reg_base = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!drvdata->reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		dev_err(dev, "failed to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	drvdata->clk = clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (IS_ERR(drvdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		error = PTR_ERR(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		dev_err(dev, "couldn't get clock %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	error = clk_prepare_enable(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		dev_err(dev, "failed to enable clock %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	serio->id.type = SERIO_8042;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	serio->write = sun4i_ps2_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	serio->open = sun4i_ps2_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	serio->close = sun4i_ps2_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	serio->port_data = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	serio->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	strlcpy(serio->name, dev_name(dev), sizeof(serio->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	strlcpy(serio->phys, dev_name(dev), sizeof(serio->phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* shutoff interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	writel(0, drvdata->reg_base + PS2_REG_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* Get IRQ for the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	drvdata->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (drvdata->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		error = drvdata->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	drvdata->serio = serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	drvdata->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	error = request_irq(drvdata->irq, sun4i_ps2_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			    DRIVER_NAME, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		dev_err(drvdata->dev, "failed to allocate interrupt %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			drvdata->irq, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	serio_register_port(serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	platform_set_drvdata(pdev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return 0;	/* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	clk_disable_unprepare(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	clk_put(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	iounmap(drvdata->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) err_free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	kfree(serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	kfree(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int sun4i_ps2_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct sun4i_ps2data *drvdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	serio_unregister_port(drvdata->serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	free_irq(drvdata->irq, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	clk_disable_unprepare(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	clk_put(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	iounmap(drvdata->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	kfree(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct of_device_id sun4i_ps2_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	{ .compatible = "allwinner,sun4i-a10-ps2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_DEVICE_TABLE(of, sun4i_ps2_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct platform_driver sun4i_ps2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.probe		= sun4i_ps2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.remove		= sun4i_ps2_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.of_match_table = sun4i_ps2_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) module_platform_driver(sun4i_ps2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_AUTHOR("Aaron.maoye <leafy.myeh@newbietech.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_DESCRIPTION("Allwinner A10/Sun4i PS/2 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_LICENSE("GPL v2");