^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SGI O2 MACE PS2 controller driver for linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002 Vivien Chappelier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/serio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/ip32/mace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/ip32/ip32_ints.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_AUTHOR("Vivien Chappelier <vivien.chappelier@linux-mips.org");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_DESCRIPTION("SGI O2 MACE PS2 controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MACE_PS2_TIMEOUT 10000 /* in 50us unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PS2_STATUS_CLOCK_SIGNAL BIT(0) /* external clock signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PS2_STATUS_CLOCK_INHIBIT BIT(1) /* clken output signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PS2_STATUS_TX_INPROGRESS BIT(2) /* transmission in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PS2_STATUS_TX_EMPTY BIT(3) /* empty transmit buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PS2_STATUS_RX_FULL BIT(4) /* full receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PS2_STATUS_RX_INPROGRESS BIT(5) /* reception in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PS2_STATUS_ERROR_PARITY BIT(6) /* parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PS2_STATUS_ERROR_FRAMING BIT(7) /* framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PS2_CONTROL_TX_CLOCK_DISABLE BIT(0) /* inhibit clock signal after TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PS2_CONTROL_TX_ENABLE BIT(1) /* transmit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PS2_CONTROL_TX_INT_ENABLE BIT(2) /* enable transmit interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PS2_CONTROL_RX_INT_ENABLE BIT(3) /* enable receive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PS2_CONTROL_RX_CLOCK_ENABLE BIT(4) /* pause reception if set to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PS2_CONTROL_RESET BIT(5) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct maceps2_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mace_ps2port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct maceps2_data port_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct serio *maceps2_port[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct platform_device *maceps2_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int maceps2_write(struct serio *dev, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct mace_ps2port *port = ((struct maceps2_data *)dev->port_data)->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int timeout = MACE_PS2_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (port->status & PS2_STATUS_TX_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) port->tx = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static irqreturn_t maceps2_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct serio *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mace_ps2port *port = ((struct maceps2_data *)dev->port_data)->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (port->status & PS2_STATUS_RX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) byte = port->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) serio_interrupt(dev, byte & 0xff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int maceps2_open(struct serio *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct maceps2_data *data = (struct maceps2_data *)dev->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (request_irq(data->irq, maceps2_interrupt, 0, "PS2 port", dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) printk(KERN_ERR "Could not allocate PS/2 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Reset port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) data->port->control = PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) data->port->control = PS2_CONTROL_RX_CLOCK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PS2_CONTROL_TX_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PS2_CONTROL_RX_INT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void maceps2_close(struct serio *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct maceps2_data *data = (struct maceps2_data *)dev->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) data->port->control = PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) free_irq(data->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct serio *maceps2_allocate_port(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct serio *serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (serio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) serio->id.type = SERIO_8042;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) serio->write = maceps2_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) serio->open = maceps2_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) serio->close = maceps2_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) snprintf(serio->name, sizeof(serio->name), "MACE PS/2 port%d", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) snprintf(serio->phys, sizeof(serio->phys), "mace/serio%d", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) serio->port_data = &port_data[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) serio->dev.parent = &maceps2_device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int maceps2_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) maceps2_port[0] = maceps2_allocate_port(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) maceps2_port[1] = maceps2_allocate_port(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!maceps2_port[0] || !maceps2_port[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) kfree(maceps2_port[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) kfree(maceps2_port[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) serio_register_port(maceps2_port[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) serio_register_port(maceps2_port[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int maceps2_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) serio_unregister_port(maceps2_port[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) serio_unregister_port(maceps2_port[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct platform_driver maceps2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = "maceps2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .probe = maceps2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .remove = maceps2_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int __init maceps2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) error = platform_driver_register(&maceps2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) maceps2_device = platform_device_alloc("maceps2", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!maceps2_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto err_unregister_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) port_data[0].port = &mace->perif.ps2.keyb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) port_data[0].irq = MACEISA_KEYB_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) port_data[1].port = &mace->perif.ps2.mouse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) port_data[1].irq = MACEISA_MOUSE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) error = platform_device_add(maceps2_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto err_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err_free_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) platform_device_put(maceps2_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err_unregister_driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) platform_driver_unregister(&maceps2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void __exit maceps2_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) platform_device_unregister(maceps2_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) platform_driver_unregister(&maceps2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) module_init(maceps2_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) module_exit(maceps2_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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