^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i8042 keyboard and mouse controller driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 1999-2004 Vojtech Pavlik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/serio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/rcupdate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i8042.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static bool i8042_nokbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param_named(nokbd, i8042_nokbd, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static bool i8042_noaux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param_named(noaux, i8042_noaux, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static bool i8042_nomux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) module_param_named(nomux, i8042_nomux, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static bool i8042_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) module_param_named(unlock, i8042_unlock, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static bool i8042_probe_defer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) module_param_named(probe_defer, i8042_probe_defer, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_PARM_DESC(probe_defer, "Allow deferred probing.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) enum i8042_controller_reset_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) I8042_RESET_NEVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) I8042_RESET_ALWAYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) I8042_RESET_ON_S2RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int i8042_set_reset(const char *val, const struct kernel_param *kp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum i8042_controller_reset_mode *arg = kp->arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bool reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) error = kstrtobool(val, &reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct kernel_param_ops param_ops_reset_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .flags = KERNEL_PARAM_OPS_FL_NOARG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .set = i8042_set_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define param_check_reset_param(name, p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __param_check(name, p, enum i8042_controller_reset_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) module_param_named(reset, i8042_reset, reset_param, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static bool i8042_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) module_param_named(direct, i8042_direct, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static bool i8042_dumbkbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static bool i8042_noloop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) module_param_named(noloop, i8042_noloop, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static bool i8042_notimeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) module_param_named(notimeout, i8042_notimeout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static bool i8042_kbdreset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) module_param_named(kbdreset, i8042_kbdreset, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static bool i8042_dritek;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) module_param_named(dritek, i8042_dritek, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static bool i8042_nopnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) module_param_named(nopnp, i8042_nopnp, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static bool i8042_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) module_param_named(debug, i8042_debug, bool, 0600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static bool i8042_unmask_kbd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static bool i8042_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static bool i8042_bypass_aux_irq_test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static char i8042_kbd_firmware_id[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static char i8042_aux_firmware_id[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct fwnode_handle *i8042_kbd_fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #include "i8042.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * i8042_lock protects serialization between i8042_command and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * the interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static DEFINE_SPINLOCK(i8042_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Writers to AUX and KBD ports as well as users issuing i8042_command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * directly should acquire i8042_mutex (by means of calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * they do not disturb each other (unfortunately in many i8042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * implementations write to one of the ports will immediately abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * command that is being processed by another port).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static DEFINE_MUTEX(i8042_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct i8042_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct serio *serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bool exists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool driver_bound;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) signed char mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define I8042_KBD_PORT_NO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define I8042_AUX_PORT_NO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define I8042_MUX_PORT_NO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct i8042_port i8042_ports[I8042_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static unsigned char i8042_initial_ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static unsigned char i8042_ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static bool i8042_mux_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static bool i8042_kbd_irq_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static bool i8042_aux_irq_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static unsigned char i8042_suppress_kbd_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct platform_device *i8042_platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct notifier_block i8042_kbd_bind_notifier_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static irqreturn_t i8042_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static bool (*i8042_platform_filter)(unsigned char data, unsigned char str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct serio *serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void i8042_lock_chip(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mutex_lock(&i8042_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) EXPORT_SYMBOL(i8042_lock_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void i8042_unlock_chip(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mutex_unlock(&i8042_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) EXPORT_SYMBOL(i8042_unlock_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct serio *serio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (i8042_platform_filter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) i8042_platform_filter = filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EXPORT_SYMBOL(i8042_install_filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct serio *port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (i8042_platform_filter != filter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) i8042_platform_filter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) EXPORT_SYMBOL(i8042_remove_filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * be ready for reading values from it / writing values to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Called always with i8042_lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int i8042_wait_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -(i == I8042_CTL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int i8042_wait_write(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -(i == I8042_CTL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * of the i8042 down the toilet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int i8042_flush(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned char data, str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) while ((str = i8042_read_status()) & I8042_STR_OBF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (count++ < I8042_BUFFER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) data = i8042_read_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dbg("%02x <- i8042 (flush, %s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * i8042_command() executes a command on the i8042. It also sends the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * parameter(s) of the commands to it, and receives the output value(s). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * parameters are to be stored in the param array, and the output is placed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * into the same array. The number of the parameters and output values is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * encoded in bits 8-11 of the command number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int __i8042_command(unsigned char *param, int command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int i, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) error = i8042_wait_write();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dbg("%02x -> i8042 (command)\n", command & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) i8042_write_command(command & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (i = 0; i < ((command >> 12) & 0xf); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) error = i8042_wait_write();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dbg(" -- i8042 (wait write timeout)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dbg("%02x -> i8042 (parameter)\n", param[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) i8042_write_data(param[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (i = 0; i < ((command >> 8) & 0xf); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) error = i8042_wait_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dbg(" -- i8042 (wait read timeout)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (command == I8042_CMD_AUX_LOOP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) !(i8042_read_status() & I8042_STR_AUXDATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dbg(" -- i8042 (auxerr)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) param[i] = i8042_read_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dbg("%02x <- i8042 (return)\n", param[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int i8042_command(unsigned char *param, int command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!i8042_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) retval = __i8042_command(param, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) EXPORT_SYMBOL(i8042_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * i8042_kbd_write() sends a byte out through the keyboard interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int i8042_kbd_write(struct serio *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!(retval = i8042_wait_write())) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dbg("%02x -> i8042 (kbd-data)\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) i8042_write_data(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * i8042_aux_write() sends a byte out through the aux interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int i8042_aux_write(struct serio *serio, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct i8042_port *port = serio->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return i8042_command(&c, port->mux == -1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) I8042_CMD_AUX_SEND :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) I8042_CMD_MUX_SEND + port->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * i8042_port_close attempts to clear AUX or KBD port state by disabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * and then re-enabling it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void i8042_port_close(struct serio *serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int irq_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int disable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const char *port_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) irq_bit = I8042_CTR_AUXINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) disable_bit = I8042_CTR_AUXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) port_name = "AUX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) irq_bit = I8042_CTR_KBDINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) disable_bit = I8042_CTR_KBDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) port_name = "KBD";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) i8042_ctr &= ~irq_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pr_warn("Can't write CTR while closing %s port\n", port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) i8042_ctr &= ~disable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) i8042_ctr |= irq_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pr_err("Can't reactivate %s port\n", port_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * See if there is any data appeared while we were messing with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * port state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) i8042_interrupt(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * i8042_start() is called by serio core when port is about to finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * registering. It will mark port as existing so i8042_interrupt can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * start sending data through it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int i8042_start(struct serio *serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct i8042_port *port = serio->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) device_set_wakeup_capable(&serio->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * On platforms using suspend-to-idle, allow the keyboard to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * wake up the system from sleep by enabling keyboard wakeups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * by default. This is consistent with keyboard wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * behavior on many platforms using suspend-to-RAM (ACPI S3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (pm_suspend_default_s2idle() &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) serio == i8042_ports[I8042_KBD_PORT_NO].serio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) device_set_wakeup_enable(&serio->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) spin_lock_irq(&i8042_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) port->exists = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spin_unlock_irq(&i8042_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * i8042_stop() marks serio port as non-existing so i8042_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * will not try to send data to the port that is about to go away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * The function is called by serio core as part of unregister procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void i8042_stop(struct serio *serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct i8042_port *port = serio->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) spin_lock_irq(&i8042_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) port->exists = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) port->serio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) spin_unlock_irq(&i8042_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * We need to make sure that interrupt handler finishes using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * our serio port before we return from this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * We synchronize with both AUX and KBD IRQs because there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * a (very unlikely) chance that AUX IRQ is raised for KBD port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * and vice versa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) synchronize_irq(I8042_AUX_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) synchronize_irq(I8042_KBD_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * i8042_filter() filters out unwanted bytes from the input data stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * It is called from i8042_interrupt and thus is running with interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * off and i8042_lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static bool i8042_filter(unsigned char data, unsigned char str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct serio *serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (unlikely(i8042_suppress_kbd_ack)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if ((~str & I8042_STR_AUXDATA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) (data == 0xfa || data == 0xfe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) i8042_suppress_kbd_ack--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dbg("Extra keyboard ACK - filtered out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dbg("Filtered out by platform filter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * i8042_interrupt() is the most important function in this driver -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * it handles the interrupts from the i8042, and sends incoming bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * to the upper layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static irqreturn_t i8042_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct i8042_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct serio *serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned char str, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int dfl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned int port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) bool filtered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) str = i8042_read_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (unlikely(~str & I8042_STR_OBF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dbg("Interrupt %d, without any data\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) data = i8042_read_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static unsigned long last_transmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static unsigned char last_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dfl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (str & I8042_STR_MUXERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dbg("MUX error, status is %02x, data is %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) str, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * When MUXERR condition is signalled the data register can only contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * it is not always the case. Some KBCs also report 0xfc when there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * nothing connected to the port while others sometimes get confused which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * port the data came from and signal error leaving the data intact. They
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * _do not_ revert to legacy mode (actually I've never seen KBC reverting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * to legacy mode yet, when we see one we'll add proper handling).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * rest assume that the data came from the same serio last byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * was transmitted (if transmission happened not too long ago).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) switch (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (time_before(jiffies, last_transmit + HZ/10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) str = last_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fallthrough; /* report timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case 0xfc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case 0xfd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) last_str = str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) last_transmit = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) port_no = (str & I8042_STR_AUXDATA) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) port = &i8042_ports[port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) serio = port->exists ? port->serio : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) port_no, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dfl & SERIO_PARITY ? ", bad parity" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dfl & SERIO_TIMEOUT ? ", timeout" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) filtered = i8042_filter(data, str, serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (likely(serio && !filtered))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) serio_interrupt(serio, data, dfl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * i8042_enable_kbd_port enables keyboard port on chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int i8042_enable_kbd_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) i8042_ctr &= ~I8042_CTR_KBDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) i8042_ctr |= I8042_CTR_KBDINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) i8042_ctr &= ~I8042_CTR_KBDINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) i8042_ctr |= I8042_CTR_KBDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pr_err("Failed to enable KBD port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * i8042_enable_aux_port enables AUX (mouse) port on chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int i8042_enable_aux_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) i8042_ctr &= ~I8042_CTR_AUXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) i8042_ctr |= I8042_CTR_AUXINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) i8042_ctr &= ~I8042_CTR_AUXINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) i8042_ctr |= I8042_CTR_AUXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pr_err("Failed to enable AUX port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * i8042_enable_mux_ports enables 4 individual AUX ports after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * the controller has been switched into Multiplexed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int i8042_enable_mux_ports(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned char param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) i8042_command(¶m, I8042_CMD_MUX_PFX + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) i8042_command(¶m, I8042_CMD_AUX_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return i8042_enable_aux_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * i8042_set_mux_mode checks whether the controller has an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * active multiplexor and puts the chip into Multiplexed (true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * or Legacy (false) mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned char param, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * Get rid of bytes in the queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) i8042_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * Internal loopback test - send three bytes, they should come back from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * mouse interface, the last should be version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) param = val = 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) param = val = multiplex ? 0x56 : 0xf6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) param = val = multiplex ? 0xa4 : 0xa5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * Workaround for interference with USB Legacy emulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * that causes a v10.12 MUX to be found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (param == 0xac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (mux_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *mux_version = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * i8042_check_mux() checks whether the controller supports the PS/2 Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Multiplexing specification by Synaptics, Phoenix, Insyde and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * LCS/Telegraphics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int i8042_check_mux(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unsigned char mux_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (i8042_set_mux_mode(true, &mux_version))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pr_info("Detected active multiplexing controller, rev %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) (mux_version >> 4) & 0xf, mux_version & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Disable all muxed ports by disabling AUX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) i8042_ctr |= I8042_CTR_AUXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) i8042_ctr &= ~I8042_CTR_AUXINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) pr_err("Failed to disable AUX port, can't use MUX\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) i8042_mux_present = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * The following is used to test AUX IRQ delivery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static struct completion i8042_aux_irq_delivered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static bool i8042_irq_being_tested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static irqreturn_t i8042_aux_test_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) unsigned char str, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) str = i8042_read_status();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (str & I8042_STR_OBF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) data = i8042_read_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dbg("%02x <- i8042 (aux_test_irq, %s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) data, str & I8042_STR_AUXDATA ? "aux" : "kbd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (i8042_irq_being_tested &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) data == 0xa5 && (str & I8042_STR_AUXDATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) complete(&i8042_aux_irq_delivered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * verifies success by readinng CTR. Used when testing for presence of AUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int i8042_toggle_aux(bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned char param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (i8042_command(¶m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* some chips need some time to set the I8042_CTR_AUXDIS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (i8042_command(¶m, I8042_CMD_CTL_RCTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (!(param & I8042_CTR_AUXDIS) == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * i8042_check_aux() applies as much paranoia as it can at detecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * the presence of an AUX interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int i8042_check_aux(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int retval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) bool irq_registered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) bool aux_loop_broken = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned char param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Get rid of bytes in the queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) i8042_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * Internal loopback test - filters out AT-type i8042's. Unfortunately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * SiS screwed up and their 5597 doesn't support the LOOP command even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * though it has an AUX port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) param = 0x5a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) retval = i8042_command(¶m, I8042_CMD_AUX_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (retval || param != 0x5a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * External connection test - filters out AT-soldered PS/2 i8042's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * 0xfa - no error on some notebooks which ignore the spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * Because it's common for chipsets to return error on perfectly functioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * AUX ports, we test for this only when the LOOP command failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (i8042_command(¶m, I8042_CMD_AUX_TEST) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) (param && param != 0xfa && param != 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * If AUX_LOOP completed without error but returned unexpected data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * mark it as broken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) aux_loop_broken = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * Bit assignment test - filters out PS/2 i8042's in AT mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (i8042_toggle_aux(false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (i8042_toggle_aux(true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * Reset keyboard (needed on some laptops to successfully detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * touchpad, e.g., some Gigabyte laptop models with Elantech
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * touchpads).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (i8042_kbdreset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) pr_warn("Attempting to reset device connected to KBD port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) i8042_kbd_write(NULL, (unsigned char) 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * used it for a PCI card or somethig else.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * Without LOOP command we can't test AUX IRQ delivery. Assume the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * is working and hope we are right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "i8042", i8042_platform_device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) irq_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (i8042_enable_aux_port())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) init_completion(&i8042_aux_irq_delivered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) i8042_irq_being_tested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) param = 0xa5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) msecs_to_jiffies(250)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * AUX IRQ was never delivered so we need to flush the controller to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * get rid of the byte we put there; otherwise keyboard may not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dbg(" -- i8042 (aux irq test timeout)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) i8042_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) retval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * Disable the interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) i8042_ctr |= I8042_CTR_AUXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) i8042_ctr &= ~I8042_CTR_AUXINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) retval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (irq_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) free_irq(I8042_AUX_IRQ, i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int i8042_controller_check(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (i8042_flush()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) pr_info("No controller found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int i8042_controller_selftest(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) unsigned char param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * We try this 5 times; on some really fragile systems this does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * take the first time...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (i8042_command(¶m, I8042_CMD_CTL_TEST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pr_err("i8042 controller selftest timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (param == I8042_RET_CTL_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dbg("i8042 controller selftest: %#x != %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) param, I8042_RET_CTL_TEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } while (i++ < 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * On x86, we don't fail entire i8042 initialization if controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * reset fails in hopes that keyboard port will still be functional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * and user will still get a working keyboard. This is especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * important on netbooks. On other arches we trust hardware more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) pr_info("giving up on controller selftest, continuing anyway...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) pr_err("i8042 controller selftest failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * i8042_controller init initializes the i8042 controller, and,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * most importantly, sets it into non-xlated mode if that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * desired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static int i8042_controller_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) unsigned char ctr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * Save the CTR for restore on unload / reboot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (n >= 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pr_err("Unable to get stable CTR read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (n != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pr_err("Can't read CTR while initializing i8042\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return i8042_probe_defer ? -EPROBE_DEFER : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) } while (n < 2 || ctr[0] != ctr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) i8042_initial_ctr = i8042_ctr = ctr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * Disable the keyboard interface and interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) i8042_ctr |= I8042_CTR_KBDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) i8042_ctr &= ~I8042_CTR_KBDINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * Handle keylock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) spin_lock_irqsave(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (~i8042_read_status() & I8042_STR_KEYLOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (i8042_unlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) i8042_ctr |= I8042_CTR_IGNKEYLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) pr_warn("Warning: Keylock active\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) spin_unlock_irqrestore(&i8042_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * If the chip is configured into nontranslated mode by the BIOS, don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * bother enabling translating and be happy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (~i8042_ctr & I8042_CTR_XLATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) i8042_direct = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * Set nontranslated mode for the kbd interface if requested by an option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * After this the kbd interface becomes a simple serial in/out, like the aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * interface is. We don't do this by default, since it can confuse notebook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * BIOSes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (i8042_direct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) i8042_ctr &= ~I8042_CTR_XLATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * Write CTR back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) pr_err("Can't write CTR while initializing i8042\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * Flush whatever accumulated while we were disabling keyboard port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) i8042_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * Reset the controller and reset CRT to the original value set by BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static void i8042_controller_reset(bool s2r_wants_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) i8042_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * Disable both KBD and AUX interfaces so they don't get in the way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pr_warn("Can't write CTR while resetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * Disable MUX mode if present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (i8042_mux_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) i8042_set_mux_mode(false, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * Reset the controller if requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (i8042_reset == I8042_RESET_ALWAYS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) i8042_controller_selftest();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * Restore the original control register setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) pr_warn("Can't restore CTR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * i8042_panic_blink() will turn the keyboard LEDs on or off and is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * when kernel panics. Flashing LEDs is useful for users running X who may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * not see the console and will help distinguishing panics from "real"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * lockups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * Note that DELAY has a limit of 10ms so we will not get stuck here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * waiting for KBC to free up even if KBD interrupt is off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static long i8042_panic_blink(int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) long delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) char led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) led = (state) ? 0x01 | 0x04 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) while (i8042_read_status() & I8042_STR_IBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dbg("%02x -> i8042 (panic blink)\n", 0xed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) i8042_suppress_kbd_ack = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) i8042_write_data(0xed); /* set leds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) while (i8042_read_status() & I8042_STR_IBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dbg("%02x -> i8042 (panic blink)\n", led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) i8042_write_data(led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #undef DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static void i8042_dritek_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) unsigned char param = 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) error = i8042_command(¶m, 0x1059);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pr_warn("Failed to enable DRITEK extension: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * Here we try to reset everything back to a state we had
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * before suspending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static int i8042_controller_resume(bool s2r_wants_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) error = i8042_controller_check();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (i8042_reset == I8042_RESET_ALWAYS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) error = i8042_controller_selftest();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * Restore original CTR value and disable all ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) i8042_ctr = i8042_initial_ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (i8042_direct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) i8042_ctr &= ~I8042_CTR_XLATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pr_warn("Can't write CTR to resume, retrying...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) pr_err("CTR write retry failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (i8042_dritek)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) i8042_dritek_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (i8042_mux_present) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) pr_warn("failed to resume active multiplexor, mouse won't work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) i8042_enable_aux_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (i8042_ports[I8042_KBD_PORT_NO].serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) i8042_enable_kbd_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) i8042_interrupt(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * Here we try to restore the original BIOS settings to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * upsetting it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int i8042_pm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (pm_suspend_via_firmware())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) i8042_controller_reset(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* Set up serio interrupts for system wakeup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) for (i = 0; i < I8042_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct serio *serio = i8042_ports[i].serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (serio && device_may_wakeup(&serio->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) enable_irq_wake(i8042_ports[i].irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static int i8042_pm_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (!pm_resume_via_firmware())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) i8042_interrupt(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int i8042_pm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) bool want_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) for (i = 0; i < I8042_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct serio *serio = i8042_ports[i].serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (serio && device_may_wakeup(&serio->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) disable_irq_wake(i8042_ports[i].irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * If platform firmware was not going to be involved in suspend, we did
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * not restore the controller state to whatever it had been at boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * time, so we do not need to do anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!pm_suspend_via_firmware())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * We only need to reset the controller if we are resuming after handing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * off control to the platform firmware, otherwise we can simply restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * the mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) want_reset = pm_resume_via_firmware();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return i8042_controller_resume(want_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int i8042_pm_thaw(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) i8042_interrupt(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static int i8042_pm_reset(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) i8042_controller_reset(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int i8042_pm_restore(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return i8042_controller_resume(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static const struct dev_pm_ops i8042_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .suspend = i8042_pm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .resume_noirq = i8042_pm_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .resume = i8042_pm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .thaw = i8042_pm_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .poweroff = i8042_pm_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .restore = i8042_pm_restore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * We need to reset the 8042 back to original mode on system shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * because otherwise BIOSes will be confused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static void i8042_shutdown(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) i8042_controller_reset(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static int i8042_create_kbd_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct serio *serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (!serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) serio->start = i8042_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) serio->stop = i8042_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) serio->close = i8042_port_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) serio->ps2_cmd_mutex = &i8042_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) serio->port_data = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) serio->dev.parent = &i8042_platform_device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) strlcpy(serio->firmware_id, i8042_kbd_firmware_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) sizeof(serio->firmware_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) set_primary_fwnode(&serio->dev, i8042_kbd_fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) port->serio = serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) port->irq = I8042_KBD_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int i8042_create_aux_port(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct serio *serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct i8042_port *port = &i8042_ports[port_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (!serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) serio->id.type = SERIO_8042;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) serio->write = i8042_aux_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) serio->start = i8042_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) serio->stop = i8042_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) serio->ps2_cmd_mutex = &i8042_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) serio->port_data = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) serio->dev.parent = &i8042_platform_device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (idx < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) strlcpy(serio->firmware_id, i8042_aux_firmware_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) sizeof(serio->firmware_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) serio->close = i8042_port_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) strlcpy(serio->firmware_id, i8042_aux_firmware_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) sizeof(serio->firmware_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) port->serio = serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) port->mux = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) port->irq = I8042_AUX_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static void i8042_free_kbd_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static void i8042_free_aux_ports(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) kfree(i8042_ports[i].serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) i8042_ports[i].serio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static void i8042_register_ports(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) for (i = 0; i < I8042_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct serio *serio = i8042_ports[i].serio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (!serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) serio->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) (unsigned long) I8042_DATA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) (unsigned long) I8042_COMMAND_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) i8042_ports[i].irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) serio_register_port(serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static void i8042_unregister_ports(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) for (i = 0; i < I8042_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (i8042_ports[i].serio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) serio_unregister_port(i8042_ports[i].serio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) i8042_ports[i].serio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static void i8042_free_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (i8042_aux_irq_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) free_irq(I8042_AUX_IRQ, i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (i8042_kbd_irq_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) free_irq(I8042_KBD_IRQ, i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) i8042_aux_irq_registered = i8042_kbd_irq_registered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static int i8042_setup_aux(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) int (*aux_enable)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (i8042_check_aux())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (i8042_nomux || i8042_check_mux()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) error = i8042_create_aux_port(-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) goto err_free_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) aux_enable = i8042_enable_aux_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) error = i8042_create_aux_port(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) goto err_free_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) aux_enable = i8042_enable_mux_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) "i8042", i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) goto err_free_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) error = aux_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) i8042_aux_irq_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) free_irq(I8042_AUX_IRQ, i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) err_free_ports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) i8042_free_aux_ports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static int i8042_setup_kbd(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) error = i8042_create_kbd_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) "i8042", i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) goto err_free_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) error = i8042_enable_kbd_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) i8042_kbd_irq_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) free_irq(I8042_KBD_IRQ, i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) err_free_port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) i8042_free_kbd_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static int i8042_kbd_bind_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct serio *serio = to_serio_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct i8042_port *port = serio->port_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (serio != i8042_ports[I8042_KBD_PORT_NO].serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) case BUS_NOTIFY_BOUND_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) port->driver_bound = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) case BUS_NOTIFY_UNBIND_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) port->driver_bound = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int i8042_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) i8042_platform_device = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (i8042_reset == I8042_RESET_ALWAYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) error = i8042_controller_selftest();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) error = i8042_controller_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (i8042_dritek)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) i8042_dritek_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (!i8042_noaux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) error = i8042_setup_aux();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (error && error != -ENODEV && error != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (!i8042_nokbd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) error = i8042_setup_kbd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * Ok, everything is ready, let's register all serio ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) i8042_register_ports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) out_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) i8042_free_aux_ports(); /* in case KBD failed but AUX not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) i8042_free_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) i8042_controller_reset(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) i8042_platform_device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static int i8042_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) i8042_unregister_ports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) i8042_free_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) i8042_controller_reset(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) i8042_platform_device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static struct platform_driver i8042_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .name = "i8042",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .pm = &i8042_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .probe = i8042_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .remove = i8042_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .shutdown = i8042_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static struct notifier_block i8042_kbd_bind_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .notifier_call = i8042_kbd_bind_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int __init i8042_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) dbg_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) err = i8042_platform_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return (err == -ENODEV) ? 0 : err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) err = i8042_controller_check();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) goto err_platform_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /* Set this before creating the dev to allow i8042_command to work right away */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) i8042_present = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) err = platform_driver_register(&i8042_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) goto err_platform_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) i8042_platform_device = platform_device_alloc("i8042", -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (!i8042_platform_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) goto err_unregister_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) err = platform_device_add(i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) goto err_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) panic_blink = i8042_panic_blink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) err_free_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) platform_device_put(i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) err_unregister_driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) platform_driver_unregister(&i8042_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) err_platform_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) i8042_platform_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static void __exit i8042_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (!i8042_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) platform_device_unregister(i8042_platform_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) platform_driver_unregister(&i8042_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) i8042_platform_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) panic_blink = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) module_init(i8042_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) module_exit(i8042_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags