^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012-2015 Synaptics Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 Zodiac Inflight Innovations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/rmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/videobuf2-v4l2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/videobuf2-vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "rmi_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define F54_NAME "rmi4_f54"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* F54 data offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define F54_REPORT_DATA_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define F54_FIFO_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define F54_NUM_TX_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define F54_NUM_RX_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * The smbus protocol can read only 32 bytes max at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * But this should be fine for i2c/spi as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define F54_REPORT_DATA_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* F54 commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define F54_GET_REPORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define F54_FORCE_CAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* F54 capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define F54_CAP_BASELINE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define F54_CAP_IMAGE8 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define F54_CAP_IMAGE16 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * enum rmi_f54_report_type - RMI4 F54 report types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @F54_8BIT_IMAGE: Normalized 8-Bit Image Report. The capacitance variance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * from baseline for each pixel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @F54_16BIT_IMAGE: Normalized 16-Bit Image Report. The capacitance variance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * from baseline for each pixel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @F54_RAW_16BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Raw 16-Bit Image Report. The raw capacitance for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * pixel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @F54_TRUE_BASELINE: True Baseline Report. The baseline capacitance for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * pixel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @F54_FULL_RAW_CAP: Full Raw Capacitance Report. The raw capacitance with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * low reference set to its minimum value and high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * reference set to its maximum value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @F54_FULL_RAW_CAP_RX_OFFSET_REMOVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Full Raw Capacitance with Receiver Offset Removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Report. Set Low reference to its minimum value and high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * references to its maximum value, then report the raw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * capacitance for each pixel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum rmi_f54_report_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) F54_REPORT_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) F54_8BIT_IMAGE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) F54_16BIT_IMAGE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) F54_RAW_16BIT_IMAGE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) F54_TRUE_BASELINE = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) F54_FULL_RAW_CAP = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) F54_FULL_RAW_CAP_RX_OFFSET_REMOVED = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) F54_MAX_REPORT_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const char * const rmi_f54_report_type_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [F54_REPORT_NONE] = "Unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [F54_8BIT_IMAGE] = "Normalized 8-Bit Image",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [F54_16BIT_IMAGE] = "Normalized 16-Bit Image",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [F54_RAW_16BIT_IMAGE] = "Raw 16-Bit Image",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [F54_TRUE_BASELINE] = "True Baseline",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [F54_FULL_RAW_CAP] = "Full Raw Capacitance",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [F54_FULL_RAW_CAP_RX_OFFSET_REMOVED]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) = "Full Raw Capacitance RX Offset Removed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct f54_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct rmi_function *fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 num_rx_electrodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 num_tx_electrodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum rmi_f54_report_type report_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 *report_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int report_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bool is_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct mutex status_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mutex data_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct workqueue_struct *workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct completion cmd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* V4L2 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_device v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_pix_format format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct video_device vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct vb2_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enum rmi_f54_report_type inputs[F54_MAX_REPORT_TYPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Basic checks on report_type to ensure we write a valid type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * to the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static bool is_f54_report_type_valid(struct f54_data *f54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum rmi_f54_report_type reptype)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) switch (reptype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case F54_8BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return f54->capabilities & F54_CAP_IMAGE8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case F54_16BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case F54_RAW_16BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return f54->capabilities & F54_CAP_IMAGE16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case F54_TRUE_BASELINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return f54->capabilities & F54_CAP_IMAGE16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case F54_FULL_RAW_CAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case F54_FULL_RAW_CAP_RX_OFFSET_REMOVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static enum rmi_f54_report_type rmi_f54_get_reptype(struct f54_data *f54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (i >= F54_MAX_REPORT_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return F54_REPORT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return f54->inputs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void rmi_f54_create_input_map(struct f54_data *f54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) enum rmi_f54_report_type reptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) for (reptype = 1; reptype < F54_MAX_REPORT_TYPE; reptype++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!is_f54_report_type_valid(f54, reptype))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) f54->inputs[i++] = reptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Remaining values are zero via kzalloc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int rmi_f54_request_report(struct rmi_function *fn, u8 report_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct f54_data *f54 = dev_get_drvdata(&fn->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct rmi_device *rmi_dev = fn->rmi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Write Report Type into F54_AD_Data0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (f54->report_type != report_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) error = rmi_write(rmi_dev, f54->fn->fd.data_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) report_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) f54->report_type = report_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Small delay after disabling interrupts to avoid race condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * in firmare. This value is a bit higher than absolutely necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Should be removed once issue is resolved in firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mutex_lock(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) error = rmi_write(rmi_dev, fn->fd.command_base_addr, F54_GET_REPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) init_completion(&f54->cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) f54->is_busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) f54->timeout = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) queue_delayed_work(f54->workqueue, &f54->work, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mutex_unlock(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static size_t rmi_f54_get_report_size(struct f54_data *f54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct rmi_device *rmi_dev = f54->fn->rmi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct rmi_driver_data *drv_data = dev_get_drvdata(&rmi_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 rx = drv_data->num_rx_electrodes ? : f54->num_rx_electrodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 tx = drv_data->num_tx_electrodes ? : f54->num_tx_electrodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) switch (rmi_f54_get_reptype(f54, f54->input)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case F54_8BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) size = rx * tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case F54_16BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case F54_RAW_16BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case F54_TRUE_BASELINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case F54_FULL_RAW_CAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case F54_FULL_RAW_CAP_RX_OFFSET_REMOVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) size = sizeof(u16) * rx * tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int rmi_f54_get_pixel_fmt(enum rmi_f54_report_type reptype, u32 *pixfmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (reptype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case F54_8BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *pixfmt = V4L2_TCH_FMT_DELTA_TD08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case F54_16BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *pixfmt = V4L2_TCH_FMT_DELTA_TD16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case F54_RAW_16BIT_IMAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case F54_TRUE_BASELINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case F54_FULL_RAW_CAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case F54_FULL_RAW_CAP_RX_OFFSET_REMOVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *pixfmt = V4L2_TCH_FMT_TU16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case F54_REPORT_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case F54_MAX_REPORT_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct v4l2_file_operations rmi_f54_video_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .open = v4l2_fh_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .release = vb2_fop_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .unlocked_ioctl = video_ioctl2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .read = vb2_fop_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .mmap = vb2_fop_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .poll = vb2_fop_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int rmi_f54_queue_setup(struct vb2_queue *q, unsigned int *nbuffers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int *nplanes, unsigned int sizes[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct device *alloc_devs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct f54_data *f54 = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (*nplanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return sizes[0] < rmi_f54_get_report_size(f54) ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *nplanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sizes[0] = rmi_f54_get_report_size(f54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void rmi_f54_buffer_queue(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct f54_data *f54 = vb2_get_drv_priv(vb->vb2_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u16 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) enum vb2_buffer_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) enum rmi_f54_report_type reptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mutex_lock(&f54->status_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) vb2_set_plane_payload(vb, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reptype = rmi_f54_get_reptype(f54, f54->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (reptype == F54_REPORT_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) state = VB2_BUF_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (f54->is_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) state = VB2_BUF_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = rmi_f54_request_report(f54->fn, reptype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(&f54->fn->dev, "Error requesting F54 report\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) state = VB2_BUF_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* get frame data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mutex_lock(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) while (f54->is_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mutex_unlock(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!wait_for_completion_timeout(&f54->cmd_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) msecs_to_jiffies(1000))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_err(&f54->fn->dev, "Timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) state = VB2_BUF_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mutex_lock(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ptr = vb2_plane_vaddr(vb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(&f54->fn->dev, "Error acquiring frame ptr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) state = VB2_BUF_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto data_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) memcpy(ptr, f54->report_data, f54->report_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) vb2_set_plane_payload(vb, 0, rmi_f54_get_report_size(f54));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) state = VB2_BUF_STATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) data_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mutex_unlock(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) vb->timestamp = ktime_get_ns();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) vbuf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) vbuf->sequence = f54->sequence++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) vb2_buffer_done(vb, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mutex_unlock(&f54->status_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void rmi_f54_stop_streaming(struct vb2_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct f54_data *f54 = vb2_get_drv_priv(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) f54->sequence = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* V4L2 structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct vb2_ops rmi_f54_queue_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .queue_setup = rmi_f54_queue_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .buf_queue = rmi_f54_buffer_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .stop_streaming = rmi_f54_stop_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .wait_prepare = vb2_ops_wait_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .wait_finish = vb2_ops_wait_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct vb2_queue rmi_f54_queue = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .buf_struct_size = sizeof(struct vb2_v4l2_buffer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .ops = &rmi_f54_queue_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .mem_ops = &vb2_vmalloc_memops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int rmi_f54_vidioc_querycap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct v4l2_capability *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct f54_data *f54 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) strlcpy(cap->driver, F54_NAME, sizeof(cap->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) strlcpy(cap->card, SYNAPTICS_INPUT_DEVICE_NAME, sizeof(cap->card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) snprintf(cap->bus_info, sizeof(cap->bus_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "rmi4:%s", dev_name(&f54->fn->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int rmi_f54_vidioc_enum_input(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct v4l2_input *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct f54_data *f54 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) enum rmi_f54_report_type reptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) reptype = rmi_f54_get_reptype(f54, i->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (reptype == F54_REPORT_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) i->type = V4L2_INPUT_TYPE_TOUCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) strlcpy(i->name, rmi_f54_report_type_names[reptype], sizeof(i->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int rmi_f54_set_input(struct f54_data *f54, unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct rmi_device *rmi_dev = f54->fn->rmi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct rmi_driver_data *drv_data = dev_get_drvdata(&rmi_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 rx = drv_data->num_rx_electrodes ? : f54->num_rx_electrodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u8 tx = drv_data->num_tx_electrodes ? : f54->num_tx_electrodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct v4l2_pix_format *f = &f54->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) enum rmi_f54_report_type reptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reptype = rmi_f54_get_reptype(f54, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (reptype == F54_REPORT_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = rmi_f54_get_pixel_fmt(reptype, &f->pixelformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) f54->input = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) f->width = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) f->height = tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) f->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) f->colorspace = V4L2_COLORSPACE_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) f->bytesperline = f->width * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) f->sizeimage = f->width * f->height * sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int rmi_f54_vidioc_s_input(struct file *file, void *priv, unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return rmi_f54_set_input(video_drvdata(file), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int rmi_f54_vidioc_g_input(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct f54_data *f54 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *i = f54->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int rmi_f54_vidioc_fmt(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct f54_data *f54 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) f->fmt.pix = f54->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int rmi_f54_vidioc_enum_fmt(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct v4l2_fmtdesc *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct f54_data *f54 = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (fmt->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fmt->pixelformat = f54->format.pixelformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int rmi_f54_vidioc_g_parm(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct v4l2_streamparm *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) a->parm.capture.readbuffers = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) a->parm.capture.timeperframe.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) a->parm.capture.timeperframe.denominator = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct v4l2_ioctl_ops rmi_f54_video_ioctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .vidioc_querycap = rmi_f54_vidioc_querycap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .vidioc_enum_fmt_vid_cap = rmi_f54_vidioc_enum_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .vidioc_s_fmt_vid_cap = rmi_f54_vidioc_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .vidioc_g_fmt_vid_cap = rmi_f54_vidioc_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .vidioc_try_fmt_vid_cap = rmi_f54_vidioc_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .vidioc_g_parm = rmi_f54_vidioc_g_parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .vidioc_enum_input = rmi_f54_vidioc_enum_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .vidioc_g_input = rmi_f54_vidioc_g_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .vidioc_s_input = rmi_f54_vidioc_s_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .vidioc_reqbufs = vb2_ioctl_reqbufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .vidioc_create_bufs = vb2_ioctl_create_bufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .vidioc_querybuf = vb2_ioctl_querybuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .vidioc_qbuf = vb2_ioctl_qbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .vidioc_dqbuf = vb2_ioctl_dqbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .vidioc_expbuf = vb2_ioctl_expbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .vidioc_streamon = vb2_ioctl_streamon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .vidioc_streamoff = vb2_ioctl_streamoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct video_device rmi_f54_video_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = "Synaptics RMI4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .fops = &rmi_f54_video_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .ioctl_ops = &rmi_f54_video_ioctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .release = video_device_release_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TOUCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) V4L2_CAP_READWRITE | V4L2_CAP_STREAMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void rmi_f54_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct f54_data *f54 = container_of(work, struct f54_data, work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct rmi_function *fn = f54->fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 fifo[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int report_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u8 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) report_size = rmi_f54_get_report_size(f54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (report_size == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(&fn->dev, "Bad report size, report type=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) f54->report_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto error; /* retry won't help */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mutex_lock(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Need to check if command has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * If not try again later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) error = rmi_read(fn->rmi_dev, f54->fn->fd.command_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_err(&fn->dev, "Failed to read back command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (command & F54_GET_REPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (time_after(jiffies, f54->timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(&fn->dev, "Get report command timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) report_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) rmi_dbg(RMI_DEBUG_FN, &fn->dev, "Get report command completed, reading data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) for (i = 0; i < report_size; i += F54_REPORT_DATA_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int size = min(F54_REPORT_DATA_SIZE, report_size - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) fifo[0] = i & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) fifo[1] = i >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) error = rmi_write_block(fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) fn->fd.data_base_addr + F54_FIFO_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) fifo, sizeof(fifo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(&fn->dev, "Failed to set fifo start offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) error = rmi_read_block(fn->rmi_dev, fn->fd.data_base_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) F54_REPORT_DATA_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) f54->report_data + i, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev_err(&fn->dev, "%s: read [%d bytes] returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __func__, size, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) f54->report_size = error ? 0 : report_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) report_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (report_size == 0 && !error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) queue_delayed_work(f54->workqueue, &f54->work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) msecs_to_jiffies(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) f54->is_busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) complete(&f54->cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mutex_unlock(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int rmi_f54_config(struct rmi_function *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct rmi_driver *drv = fn->rmi_dev->driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) drv->clear_irq_bits(fn->rmi_dev, fn->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int rmi_f54_detect(struct rmi_function *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct f54_data *f54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) f54 = dev_get_drvdata(&fn->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) error = rmi_read_block(fn->rmi_dev, fn->fd.query_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_err(&fn->dev, "%s: Failed to query F54 properties\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) f54->num_rx_electrodes = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) f54->num_tx_electrodes = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) f54->capabilities = buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) f54->clock_rate = buf[3] | (buf[4] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) f54->family = buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 num_rx_electrodes: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) f54->num_rx_electrodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 num_tx_electrodes: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) f54->num_tx_electrodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 capabilities: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) f54->capabilities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 clock rate: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) f54->clock_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) rmi_dbg(RMI_DEBUG_FN, &fn->dev, "F54 family: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) f54->family);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) f54->is_busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int rmi_f54_probe(struct rmi_function *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct f54_data *f54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u8 rx, tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) f54 = devm_kzalloc(&fn->dev, sizeof(struct f54_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!f54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) f54->fn = fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_set_drvdata(&fn->dev, f54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ret = rmi_f54_detect(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mutex_init(&f54->data_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mutex_init(&f54->status_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) rx = f54->num_rx_electrodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) tx = f54->num_tx_electrodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) f54->report_data = devm_kzalloc(&fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) array3_size(tx, rx, sizeof(u16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (f54->report_data == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) INIT_DELAYED_WORK(&f54->work, rmi_f54_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) f54->workqueue = create_singlethread_workqueue("rmi4-poller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!f54->workqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) rmi_f54_create_input_map(f54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) rmi_f54_set_input(f54, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* register video device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) strlcpy(f54->v4l2.name, F54_NAME, sizeof(f54->v4l2.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = v4l2_device_register(&fn->dev, &f54->v4l2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(&fn->dev, "Unable to register video dev.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) goto remove_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* initialize the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mutex_init(&f54->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) f54->queue = rmi_f54_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) f54->queue.drv_priv = f54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) f54->queue.lock = &f54->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) f54->queue.dev = &fn->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ret = vb2_queue_init(&f54->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) goto remove_v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) f54->vdev = rmi_f54_video_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) f54->vdev.v4l2_dev = &f54->v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) f54->vdev.lock = &f54->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) f54->vdev.vfl_dir = VFL_DIR_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) f54->vdev.queue = &f54->queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) video_set_drvdata(&f54->vdev, f54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = video_register_device(&f54->vdev, VFL_TYPE_TOUCH, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_err(&fn->dev, "Unable to register video subdevice.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) goto remove_v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) remove_v4l2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) v4l2_device_unregister(&f54->v4l2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) remove_wq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) cancel_delayed_work_sync(&f54->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) flush_workqueue(f54->workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) destroy_workqueue(f54->workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static void rmi_f54_remove(struct rmi_function *fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct f54_data *f54 = dev_get_drvdata(&fn->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) video_unregister_device(&f54->vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) v4l2_device_unregister(&f54->v4l2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) destroy_workqueue(f54->workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct rmi_function_handler rmi_f54_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .name = F54_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .func = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .probe = rmi_f54_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .config = rmi_f54_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .remove = rmi_f54_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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