^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, Zodiac Inflight Innovations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2007-2016, Synaptics Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Alexandra Chin <alexandra.chin@tw.synaptics.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Scott Lin <scott.lin@tw.synaptics.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "rmi_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "rmi_f34.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int rmi_f34v7_read_flash_status(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u8 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) f34->fn->fd.data_base_addr + f34->v7.off.flash_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) &status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) sizeof(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "%s: Error %d reading flash status\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) f34->v7.in_bl_mode = status >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) f34->v7.flash_status = status & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (f34->v7.flash_status != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dev_err(&f34->fn->dev, "%s: status=%d, command=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __func__, f34->v7.flash_status, f34->v7.command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) f34->fn->fd.data_base_addr + f34->v7.off.flash_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) &command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) sizeof(command));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dev_err(&f34->fn->dev, "%s: Failed to read flash command\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) f34->v7.command = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int rmi_f34v7_wait_for_idle(struct f34_data *f34, int timeout_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) timeout = msecs_to_jiffies(timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (!wait_for_completion_timeout(&f34->v7.cmd_done, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_warn(&f34->fn->dev, "%s: Timed out waiting for idle status\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int rmi_f34v7_write_command_single_transaction(struct f34_data *f34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct f34v7_data_1_5 data_1_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) base = f34->fn->fd.data_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) memset(&data_1_5, 0, sizeof(data_1_5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case v7_CMD_ERASE_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) data_1_5.partition_id = CORE_CODE_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) data_1_5.command = CMD_V7_ERASE_AP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case v7_CMD_ERASE_UI_FIRMWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) data_1_5.partition_id = CORE_CODE_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) data_1_5.command = CMD_V7_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case v7_CMD_ERASE_BL_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) data_1_5.partition_id = GLOBAL_PARAMETERS_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) data_1_5.command = CMD_V7_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case v7_CMD_ERASE_UI_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data_1_5.partition_id = CORE_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) data_1_5.command = CMD_V7_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case v7_CMD_ERASE_DISP_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) data_1_5.partition_id = DISPLAY_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) data_1_5.command = CMD_V7_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case v7_CMD_ERASE_FLASH_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) data_1_5.partition_id = FLASH_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) data_1_5.command = CMD_V7_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case v7_CMD_ERASE_GUEST_CODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) data_1_5.partition_id = GUEST_CODE_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) data_1_5.command = CMD_V7_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case v7_CMD_ENABLE_FLASH_PROG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) data_1_5.partition_id = BOOTLOADER_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) data_1_5.command = CMD_V7_ENTER_BL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) data_1_5.payload[0] = f34->bootloader_id[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) data_1_5.payload[1] = f34->bootloader_id[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) base + f34->v7.off.partition_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &data_1_5, sizeof(data_1_5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "%s: Failed to write single transaction command\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int rmi_f34v7_write_command(struct f34_data *f34, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) base = f34->fn->fd.data_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case v7_CMD_WRITE_FW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case v7_CMD_WRITE_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case v7_CMD_WRITE_GUEST_CODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) command = CMD_V7_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case v7_CMD_READ_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) command = CMD_V7_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case v7_CMD_ERASE_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) command = CMD_V7_ERASE_AP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case v7_CMD_ERASE_UI_FIRMWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case v7_CMD_ERASE_BL_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case v7_CMD_ERASE_UI_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case v7_CMD_ERASE_DISP_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case v7_CMD_ERASE_FLASH_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case v7_CMD_ERASE_GUEST_CODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) command = CMD_V7_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case v7_CMD_ENABLE_FLASH_PROG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) command = CMD_V7_ENTER_BL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) f34->v7.command = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case v7_CMD_ERASE_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case v7_CMD_ERASE_UI_FIRMWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case v7_CMD_ERASE_BL_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case v7_CMD_ERASE_UI_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case v7_CMD_ERASE_DISP_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case v7_CMD_ERASE_FLASH_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case v7_CMD_ERASE_GUEST_CODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case v7_CMD_ENABLE_FLASH_PROG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = rmi_f34v7_write_command_single_transaction(f34, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: writing cmd %02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __func__, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) base + f34->v7.off.flash_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) &command, sizeof(command));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(&f34->fn->dev, "%s: Failed to write flash command\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int rmi_f34v7_write_partition_id(struct f34_data *f34, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 partition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) base = f34->fn->fd.data_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case v7_CMD_WRITE_FW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) partition = CORE_CODE_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case v7_CMD_WRITE_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case v7_CMD_READ_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (f34->v7.config_area == v7_UI_CONFIG_AREA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) partition = CORE_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else if (f34->v7.config_area == v7_DP_CONFIG_AREA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) partition = DISPLAY_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else if (f34->v7.config_area == v7_PM_CONFIG_AREA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) partition = GUEST_SERIALIZATION_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else if (f34->v7.config_area == v7_BL_CONFIG_AREA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) partition = GLOBAL_PARAMETERS_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else if (f34->v7.config_area == v7_FLASH_CONFIG_AREA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) partition = FLASH_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case v7_CMD_WRITE_GUEST_CODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) partition = GUEST_CODE_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case v7_CMD_ERASE_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) partition = CORE_CODE_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case v7_CMD_ERASE_BL_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) partition = GLOBAL_PARAMETERS_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case v7_CMD_ERASE_UI_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) partition = CORE_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case v7_CMD_ERASE_DISP_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) partition = DISPLAY_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case v7_CMD_ERASE_FLASH_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) partition = FLASH_CONFIG_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case v7_CMD_ERASE_GUEST_CODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) partition = GUEST_CODE_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case v7_CMD_ENABLE_FLASH_PROG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) partition = BOOTLOADER_PARTITION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) base + f34->v7.off.partition_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) &partition, sizeof(partition));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(&f34->fn->dev, "%s: Failed to write partition ID\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int rmi_f34v7_read_partition_table(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __le16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u16 block_number = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) base = f34->fn->fd.data_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) f34->v7.config_area = v7_FLASH_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = rmi_f34v7_write_partition_id(f34, v7_CMD_READ_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) base + f34->v7.off.block_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) &block_number, sizeof(block_number));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) put_unaligned_le16(f34->v7.flash_config_length, &length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) base + f34->v7.off.transfer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &length, sizeof(length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(&f34->fn->dev, "%s: Failed to write transfer length\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = rmi_f34v7_write_command(f34, v7_CMD_READ_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(&f34->fn->dev, "%s: Failed to write command\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) timeout = msecs_to_jiffies(F34_WRITE_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) rmi_f34v7_read_flash_status(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (f34->v7.command == v7_CMD_IDLE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) f34->v7.flash_status == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) base + f34->v7.off.payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) f34->v7.read_config_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) f34->v7.partition_table_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_err(&f34->fn->dev, "%s: Failed to read block data\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void rmi_f34v7_parse_partition_table(struct f34_data *f34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) const void *partition_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct block_count *blkcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct physical_address *phyaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u16 partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u16 physical_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) const struct partition_table *ptable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < f34->v7.partitions; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) index = i * 8 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ptable = partition_table + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) partition_length = le16_to_cpu(ptable->partition_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) physical_address = le16_to_cpu(ptable->start_physical_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "%s: Partition entry %d: %*ph\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __func__, i, sizeof(struct partition_table), ptable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) switch (ptable->partition_id & 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case CORE_CODE_PARTITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) blkcount->ui_firmware = partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) phyaddr->ui_firmware = physical_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "%s: Core code block count: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __func__, blkcount->ui_firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case CORE_CONFIG_PARTITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) blkcount->ui_config = partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) phyaddr->ui_config = physical_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "%s: Core config block count: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __func__, blkcount->ui_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case DISPLAY_CONFIG_PARTITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) blkcount->dp_config = partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) phyaddr->dp_config = physical_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "%s: Display config block count: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __func__, blkcount->dp_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case FLASH_CONFIG_PARTITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) blkcount->fl_config = partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "%s: Flash config block count: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __func__, blkcount->fl_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case GUEST_CODE_PARTITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) blkcount->guest_code = partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) phyaddr->guest_code = physical_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "%s: Guest code block count: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __func__, blkcount->guest_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case GUEST_SERIALIZATION_PARTITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) blkcount->pm_config = partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "%s: Guest serialization block count: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __func__, blkcount->pm_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case GLOBAL_PARAMETERS_PARTITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) blkcount->bl_config = partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "%s: Global parameters block count: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) __func__, blkcount->bl_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case DEVICE_CONFIG_PARTITION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) blkcount->lockdown = partition_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "%s: Device config block count: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __func__, blkcount->lockdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int rmi_f34v7_read_queries_bl_version(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 query_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct f34v7_query_1_7 query_1_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) base = f34->fn->fd.query_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &query_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sizeof(query_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "%s: Failed to read query 0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) offset = (query_0 & 0x7) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) base + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) &query_1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) sizeof(query_1_7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) f34->bootloader_id[0] = query_1_7.bl_minor_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) f34->bootloader_id[1] = query_1_7.bl_major_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Bootloader V%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) f34->bootloader_id[1], f34->bootloader_id[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int rmi_f34v7_read_queries(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 *ptable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u8 query_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct f34v7_query_1_7 query_1_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) base = f34->fn->fd.query_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) &query_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sizeof(query_0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "%s: Failed to read query 0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) offset = (query_0 & 0x07) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) base + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &query_1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) sizeof(query_1_7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) f34->bootloader_id[0] = query_1_7.bl_minor_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) f34->bootloader_id[1] = query_1_7.bl_major_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) f34->v7.block_size = le16_to_cpu(query_1_7.block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) f34->v7.flash_config_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) le16_to_cpu(query_1_7.flash_config_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) f34->v7.payload_length = le16_to_cpu(query_1_7.payload_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.block_size = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) __func__, f34->v7.block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) f34->v7.off.flash_status = V7_FLASH_STATUS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) f34->v7.off.partition_id = V7_PARTITION_ID_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) f34->v7.off.block_number = V7_BLOCK_NUMBER_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) f34->v7.off.transfer_length = V7_TRANSFER_LENGTH_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) f34->v7.off.flash_cmd = V7_COMMAND_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) f34->v7.off.payload = V7_PAYLOAD_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) f34->v7.has_display_cfg = query_1_7.partition_support[1] & HAS_DISP_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) f34->v7.has_guest_code =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) query_1_7.partition_support[1] & HAS_GUEST_CODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (query_0 & HAS_CONFIG_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 f34_ctrl[CONFIG_ID_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) f34->fn->fd.control_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) f34_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sizeof(f34_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Eat leading zeros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) for (i = 0; i < sizeof(f34_ctrl) - 1 && !f34_ctrl[i]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Empty */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) snprintf(f34->configuration_id, sizeof(f34->configuration_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "%*phN", (int)sizeof(f34_ctrl) - i, f34_ctrl + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Configuration ID: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) f34->configuration_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) f34->v7.partitions = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (i = 0; i < sizeof(query_1_7.partition_support); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) f34->v7.partitions += hweight8(query_1_7.partition_support[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: Supported partitions: %*ph\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __func__, sizeof(query_1_7.partition_support),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) query_1_7.partition_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) f34->v7.partition_table_bytes = f34->v7.partitions * 8 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) f34->v7.partition_table_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!f34->v7.read_config_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) f34->v7.read_config_buf_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) f34->v7.read_config_buf_size = f34->v7.partition_table_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ptable = f34->v7.read_config_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = rmi_f34v7_read_partition_table(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_err(&f34->fn->dev, "%s: Failed to read partition table\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) rmi_f34v7_parse_partition_table(f34, ptable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) &f34->v7.blkcount, &f34->v7.phyaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int rmi_f34v7_check_ui_firmware_size(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u16 block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) block_count = f34->v7.img.ui_firmware.size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) f34->update_size += block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (block_count != f34->v7.blkcount.ui_firmware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "UI firmware size mismatch: %d != %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) block_count, f34->v7.blkcount.ui_firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int rmi_f34v7_check_ui_config_size(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u16 block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) block_count = f34->v7.img.ui_config.size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) f34->update_size += block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (block_count != f34->v7.blkcount.ui_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(&f34->fn->dev, "UI config size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int rmi_f34v7_check_dp_config_size(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u16 block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) block_count = f34->v7.img.dp_config.size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) f34->update_size += block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (block_count != f34->v7.blkcount.dp_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_err(&f34->fn->dev, "Display config size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int rmi_f34v7_check_guest_code_size(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u16 block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) block_count = f34->v7.img.guest_code.size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) f34->update_size += block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (block_count != f34->v7.blkcount.guest_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_err(&f34->fn->dev, "Guest code size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int rmi_f34v7_check_bl_config_size(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u16 block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) block_count = f34->v7.img.bl_config.size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) f34->update_size += block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (block_count != f34->v7.blkcount.bl_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dev_err(&f34->fn->dev, "Bootloader config size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int rmi_f34v7_erase_config(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_info(&f34->fn->dev, "Erasing config...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) switch (f34->v7.config_area) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case v7_UI_CONFIG_AREA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case v7_DP_CONFIG_AREA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_DISP_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) case v7_BL_CONFIG_AREA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_BL_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int rmi_f34v7_erase_guest_code(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_info(&f34->fn->dev, "Erasing guest code...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_GUEST_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int rmi_f34v7_erase_all(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_info(&f34->fn->dev, "Erasing firmware...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) f34->v7.config_area = v7_UI_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = rmi_f34v7_erase_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (f34->v7.has_display_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) f34->v7.config_area = v7_DP_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = rmi_f34v7_erase_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (f34->v7.new_partition_table && f34->v7.has_guest_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = rmi_f34v7_erase_guest_code(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int rmi_f34v7_read_blocks(struct f34_data *f34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u16 block_cnt, u8 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) __le16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u16 transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u16 max_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u16 remaining = block_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u16 block_number = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u16 index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) base = f34->fn->fd.data_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = rmi_f34v7_write_partition_id(f34, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) base + f34->v7.off.block_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) &block_number, sizeof(block_number));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) max_transfer = min(f34->v7.payload_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (u16)(PAGE_SIZE / f34->v7.block_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) transfer = min(remaining, max_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) put_unaligned_le16(transfer, &length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) base + f34->v7.off.transfer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) &length, sizeof(length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "%s: Write transfer length fail (%d remaining)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) __func__, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = rmi_f34v7_write_command(f34, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) base + f34->v7.off.payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) &f34->v7.read_config_buf[index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) transfer * f34->v7.block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "%s: Read block failed (%d blks remaining)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) __func__, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) index += (transfer * f34->v7.block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) remaining -= transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) } while (remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int rmi_f34v7_write_f34v7_blocks(struct f34_data *f34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) const void *block_ptr, u16 block_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u8 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __le16 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u16 transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u16 max_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u16 remaining = block_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u16 block_number = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) base = f34->fn->fd.data_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = rmi_f34v7_write_partition_id(f34, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) base + f34->v7.off.block_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &block_number, sizeof(block_number));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (f34->v7.payload_length > (PAGE_SIZE / f34->v7.block_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) max_transfer = PAGE_SIZE / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) max_transfer = f34->v7.payload_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) transfer = min(remaining, max_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) put_unaligned_le16(transfer, &length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) base + f34->v7.off.transfer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &length, sizeof(length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "%s: Write transfer length fail (%d remaining)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __func__, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret = rmi_f34v7_write_command(f34, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = rmi_write_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) base + f34->v7.off.payload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) block_ptr, transfer * f34->v7.block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) "%s: Failed writing data (%d blks remaining)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) __func__, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) block_ptr += (transfer * f34->v7.block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) remaining -= transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) f34->update_progress += transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) f34->update_status = (f34->update_progress * 100) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) f34->update_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) } while (remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int rmi_f34v7_write_config(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.config_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) f34->v7.config_block_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) v7_CMD_WRITE_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int rmi_f34v7_write_ui_config(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) f34->v7.config_area = v7_UI_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) f34->v7.config_data = f34->v7.img.ui_config.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) f34->v7.config_size = f34->v7.img.ui_config.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return rmi_f34v7_write_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static int rmi_f34v7_write_dp_config(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) f34->v7.config_area = v7_DP_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) f34->v7.config_data = f34->v7.img.dp_config.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) f34->v7.config_size = f34->v7.img.dp_config.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return rmi_f34v7_write_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int rmi_f34v7_write_guest_code(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.guest_code.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) f34->v7.img.guest_code.size /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) f34->v7.block_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) v7_CMD_WRITE_GUEST_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int rmi_f34v7_write_flash_config(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) f34->v7.config_area = v7_FLASH_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) f34->v7.config_data = f34->v7.img.fl_config.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) f34->v7.config_size = f34->v7.img.fl_config.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (f34->v7.config_block_count != f34->v7.blkcount.fl_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev_err(&f34->fn->dev, "%s: Flash config size mismatch\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_FLASH_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) "%s: Erase flash config command written\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = rmi_f34v7_wait_for_idle(f34, F34_WRITE_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = rmi_f34v7_write_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int rmi_f34v7_write_partition_table(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u16 block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) block_count = f34->v7.blkcount.bl_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) f34->v7.config_area = v7_BL_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) f34->v7.config_size = f34->v7.block_size * block_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) devm_kfree(&f34->fn->dev, f34->v7.read_config_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) f34->v7.config_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!f34->v7.read_config_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) f34->v7.read_config_buf_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) f34->v7.read_config_buf_size = f34->v7.config_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = rmi_f34v7_read_blocks(f34, block_count, v7_CMD_READ_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = rmi_f34v7_erase_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = rmi_f34v7_write_flash_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) f34->v7.config_area = v7_BL_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) f34->v7.config_data = f34->v7.read_config_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) f34->v7.config_size = f34->v7.img.bl_config.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret = rmi_f34v7_write_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int rmi_f34v7_write_firmware(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u16 blk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) blk_count = f34->v7.img.ui_firmware.size / f34->v7.block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.ui_firmware.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) blk_count, v7_CMD_WRITE_FW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static void rmi_f34v7_compare_partition_tables(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (f34->v7.phyaddr.ui_firmware != f34->v7.img.phyaddr.ui_firmware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) f34->v7.new_partition_table = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (f34->v7.phyaddr.ui_config != f34->v7.img.phyaddr.ui_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) f34->v7.new_partition_table = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (f34->v7.has_display_cfg &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) f34->v7.phyaddr.dp_config != f34->v7.img.phyaddr.dp_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) f34->v7.new_partition_table = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (f34->v7.has_guest_code &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) f34->v7.phyaddr.guest_code != f34->v7.img.phyaddr.guest_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) f34->v7.new_partition_table = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) f34->v7.new_partition_table = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static void rmi_f34v7_parse_img_header_10_bl_container(struct f34_data *f34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) const void *image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) int num_of_containers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) unsigned int container_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) const void *content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) const struct container_descriptor *descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) num_of_containers = f34->v7.img.bootloader.size / 4 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) for (i = 1; i <= num_of_containers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) addr = get_unaligned_le32(f34->v7.img.bootloader.data + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) descriptor = image + addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) container_id = le16_to_cpu(descriptor->container_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) content = image + le32_to_cpu(descriptor->content_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) length = le32_to_cpu(descriptor->content_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) switch (container_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) case BL_CONFIG_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) case GLOBAL_PARAMETERS_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) f34->v7.img.bl_config.data = content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) f34->v7.img.bl_config.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) case BL_LOCKDOWN_INFO_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) case DEVICE_CONFIG_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) f34->v7.img.lockdown.data = content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) f34->v7.img.lockdown.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static void rmi_f34v7_parse_image_header_10(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned int num_of_containers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) unsigned int container_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) const void *image = f34->v7.image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) const u8 *content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) const struct container_descriptor *descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) const struct image_header_10 *header = image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) f34->v7.img.checksum = le32_to_cpu(header->checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.img.checksum=%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) __func__, f34->v7.img.checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* address of top level container */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) offset = le32_to_cpu(header->top_level_container_start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) descriptor = image + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* address of top level container content */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) offset = le32_to_cpu(descriptor->content_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) num_of_containers = le32_to_cpu(descriptor->content_length) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) for (i = 0; i < num_of_containers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) addr = get_unaligned_le32(image + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) descriptor = image + addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) container_id = le16_to_cpu(descriptor->container_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) content = image + le32_to_cpu(descriptor->content_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) length = le32_to_cpu(descriptor->content_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) "%s: container_id=%d, length=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) container_id, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) switch (container_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case UI_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) case CORE_CODE_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) f34->v7.img.ui_firmware.data = content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) f34->v7.img.ui_firmware.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case UI_CONFIG_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case CORE_CONFIG_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) f34->v7.img.ui_config.data = content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) f34->v7.img.ui_config.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case BL_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) f34->v7.img.bl_version = *content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) f34->v7.img.bootloader.data = content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) f34->v7.img.bootloader.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) rmi_f34v7_parse_img_header_10_bl_container(f34, image);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case GUEST_CODE_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) f34->v7.img.contains_guest_code = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) f34->v7.img.guest_code.data = content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) f34->v7.img.guest_code.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) case DISPLAY_CONFIG_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) f34->v7.img.contains_display_cfg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) f34->v7.img.dp_config.data = content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) f34->v7.img.dp_config.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case FLASH_CONFIG_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) f34->v7.img.contains_flash_config = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) f34->v7.img.fl_config.data = content;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) f34->v7.img.fl_config.size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) case GENERAL_INFORMATION_CONTAINER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) f34->v7.img.contains_firmware_id = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) f34->v7.img.firmware_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) get_unaligned_le32(content + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static int rmi_f34v7_parse_image_info(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) const struct image_header_10 *header = f34->v7.image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) memset(&f34->v7.img, 0x00, sizeof(f34->v7.img));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "%s: header->major_header_version = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) __func__, header->major_header_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) switch (header->major_header_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) case IMAGE_HEADER_VERSION_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) rmi_f34v7_parse_image_header_10(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dev_err(&f34->fn->dev, "Unsupported image file format %02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) header->major_header_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!f34->v7.img.contains_flash_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev_err(&f34->fn->dev, "%s: No flash config in fw image\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) rmi_f34v7_parse_partition_table(f34, f34->v7.img.fl_config.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) &f34->v7.img.blkcount, &f34->v7.img.phyaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) rmi_f34v7_compare_partition_tables(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) int rmi_f34v7_do_reflash(struct f34_data *f34, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) f34->fn->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) rmi_f34v7_read_queries_bl_version(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) f34->v7.image = fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) f34->update_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) f34->update_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret = rmi_f34v7_parse_image_info(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (!f34->v7.new_partition_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret = rmi_f34v7_check_ui_firmware_size(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret = rmi_f34v7_check_ui_config_size(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (f34->v7.has_display_cfg &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) f34->v7.img.contains_display_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ret = rmi_f34v7_check_dp_config_size(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret = rmi_f34v7_check_guest_code_size(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ret = rmi_f34v7_check_bl_config_size(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ret = rmi_f34v7_erase_all(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (f34->v7.new_partition_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ret = rmi_f34v7_write_partition_table(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_info(&f34->fn->dev, "%s: Partition table programmed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dev_info(&f34->fn->dev, "Writing firmware (%d bytes)...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) f34->v7.img.ui_firmware.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = rmi_f34v7_write_firmware(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dev_info(&f34->fn->dev, "Writing config (%d bytes)...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) f34->v7.img.ui_config.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) f34->v7.config_area = v7_UI_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret = rmi_f34v7_write_ui_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (f34->v7.has_display_cfg && f34->v7.img.contains_display_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_info(&f34->fn->dev, "Writing display config...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = rmi_f34v7_write_dp_config(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (f34->v7.new_partition_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_info(&f34->fn->dev, "Writing guest code...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ret = rmi_f34v7_write_guest_code(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static int rmi_f34v7_enter_flash_prog(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret = rmi_f34v7_read_flash_status(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (f34->v7.in_bl_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = rmi_f34v7_write_command(f34, v7_CMD_ENABLE_FLASH_PROG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) int rmi_f34v7_start_reflash(struct f34_data *f34, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) f34->v7.config_area = v7_UI_CONFIG_AREA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) f34->v7.image = fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ret = rmi_f34v7_parse_image_info(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!f34->v7.force_update && f34->v7.new_partition_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_err(&f34->fn->dev, "%s: Partition table mismatch\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dev_info(&f34->fn->dev, "Firmware image OK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ret = rmi_f34v7_read_flash_status(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (f34->v7.in_bl_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) dev_info(&f34->fn->dev, "%s: Device in bootloader mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) rmi_f34v7_enter_flash_prog(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) int rmi_f34v7_probe(struct f34_data *f34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* Read bootloader version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = rmi_read_block(f34->fn->rmi_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) f34->fn->fd.query_base_addr + V7_BOOTLOADER_ID_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) f34->bootloader_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) sizeof(f34->bootloader_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev_err(&f34->fn->dev, "%s: Failed to read bootloader ID\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (f34->bootloader_id[1] == '5') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) f34->bl_version = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) } else if (f34->bootloader_id[1] == '6') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) f34->bl_version = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) } else if (f34->bootloader_id[1] == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) f34->bl_version = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) } else if (f34->bootloader_id[1] == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) f34->bl_version = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dev_err(&f34->fn->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) "%s: Unrecognized bootloader version: %d (%c) %d (%c)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) f34->bootloader_id[0], f34->bootloader_id[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) f34->bootloader_id[1], f34->bootloader_id[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) memset(&f34->v7.blkcount, 0x00, sizeof(f34->v7.blkcount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) memset(&f34->v7.phyaddr, 0x00, sizeof(f34->v7.phyaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) init_completion(&f34->v7.cmd_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ret = rmi_f34v7_read_queries(f34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) f34->v7.force_update = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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