^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PXA930 track ball mouse driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2008-02-28: Yong Yao <yaoyong@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * initial version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_data/mouse-pxa930_trkball.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Trackball Controller Register Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TBCR (0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TBCNTR (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TBSBC (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TBCR_TBRST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TBCR_TBSB (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TBCR_Y_FLT(n) (((n) & 0xf) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TBCR_X_FLT(n) (((n) & 0xf) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TBCNTR_YM(n) (((n) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TBCNTR_YP(n) (((n) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TBCNTR_XM(n) (((n) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TBCNTR_XP(n) ((n) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TBSBC_TBSBC (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pxa930_trkball {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pxa930_trkball_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Memory Mapped Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static irqreturn_t pxa930_trkball_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct pxa930_trkball *trkball = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct input_dev *input = trkball->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int tbcntr, x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* According to the spec software must read TBCNTR twice:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * if the read value is the same, the reading is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) tbcntr = __raw_readl(trkball->mmio_base + TBCNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (tbcntr == __raw_readl(trkball->mmio_base + TBCNTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) x = (TBCNTR_XP(tbcntr) - TBCNTR_XM(tbcntr)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) y = (TBCNTR_YP(tbcntr) - TBCNTR_YM(tbcntr)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) input_report_rel(input, REL_X, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) input_report_rel(input, REL_Y, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) input_sync(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __raw_writel(0, trkball->mmio_base + TBSBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* For TBCR, we need to wait for a while to make sure it has been modified. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int write_tbcr(struct pxa930_trkball *trkball, int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int i = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __raw_writel(v, trkball->mmio_base + TBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) while (--i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (__raw_readl(trkball->mmio_base + TBCR) == v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_err("%s: timed out writing TBCR(%x)!\n", __func__, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void pxa930_trkball_config(struct pxa930_trkball *trkball)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint32_t tbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* According to spec, need to write the filters of x,y to 0xf first! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tbcr = __raw_readl(trkball->mmio_base + TBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) write_tbcr(trkball, tbcr | TBCR_X_FLT(0xf) | TBCR_Y_FLT(0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) write_tbcr(trkball, TBCR_X_FLT(trkball->pdata->x_filter) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) TBCR_Y_FLT(trkball->pdata->y_filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* According to spec, set TBCR_TBRST first, before clearing it! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tbcr = __raw_readl(trkball->mmio_base + TBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) write_tbcr(trkball, tbcr | TBCR_TBRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) write_tbcr(trkball, tbcr & ~TBCR_TBRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __raw_writel(0, trkball->mmio_base + TBSBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pr_debug("%s: final TBCR=%x!\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __raw_readl(trkball->mmio_base + TBCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int pxa930_trkball_open(struct input_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pxa930_trkball *trkball = input_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pxa930_trkball_config(trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void pxa930_trkball_disable(struct pxa930_trkball *trkball)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint32_t tbcr = __raw_readl(trkball->mmio_base + TBCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Held in reset, gate the 32-KHz input clock off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) write_tbcr(trkball, tbcr | TBCR_TBRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void pxa930_trkball_close(struct input_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct pxa930_trkball *trkball = input_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pxa930_trkball_disable(trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int pxa930_trkball_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct pxa930_trkball *trkball;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int irq, error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(&pdev->dev, "failed to get register memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) trkball = kzalloc(sizeof(struct pxa930_trkball), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!trkball)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) trkball->pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!trkball->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(&pdev->dev, "no platform data defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) trkball->mmio_base = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!trkball->mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_err(&pdev->dev, "failed to ioremap registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) error = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* held the module in reset, will be enabled in open() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pxa930_trkball_disable(trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) error = request_irq(irq, pxa930_trkball_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pdev->name, trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err(&pdev->dev, "failed to request irq: %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto failed_free_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) platform_set_drvdata(pdev, trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) input = input_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(&pdev->dev, "failed to allocate input device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) goto failed_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) input->name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) input->id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) input->open = pxa930_trkball_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) input->close = pxa930_trkball_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) input->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) input_set_drvdata(input, trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) trkball->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) input_set_capability(input, EV_REL, REL_X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) input_set_capability(input, EV_REL, REL_Y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) error = input_register_device(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(&pdev->dev, "unable to register input device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto failed_free_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) failed_free_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) input_free_device(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) failed_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) free_irq(irq, trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) failed_free_io:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) iounmap(trkball->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) kfree(trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int pxa930_trkball_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct pxa930_trkball *trkball = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) input_unregister_device(trkball->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) free_irq(irq, trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) iounmap(trkball->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) kfree(trkball);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct platform_driver pxa930_trkball_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "pxa930-trkball",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .probe = pxa930_trkball_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .remove = pxa930_trkball_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) module_platform_driver(pxa930_trkball_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_AUTHOR("Yong Yao <yaoyong@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_DESCRIPTION("PXA930 Trackball Mouse Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags