Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Cypress APA trackpad with I2C interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Dudley Du <dudl@cypress.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2014-2015 Cypress Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * License.  See the file COPYING in the main directory of this archive for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #ifndef _CYAPA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define _CYAPA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* APA trackpad firmware generation number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CYAPA_GEN_UNKNOWN   0x00   /* unknown protocol. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CYAPA_GEN3   0x03   /* support MT-protocol B with tracking ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CYAPA_GEN5   0x05   /* support TrueTouch GEN5 trackpad device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CYAPA_GEN6   0x06   /* support TrueTouch GEN6 trackpad device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CYAPA_NAME   "Cypress APA Trackpad (cyapa)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Macros for SMBus communication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SMBUS_READ  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SMBUS_WRITE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SMBUS_ENCODE_IDX(cmd, idx) ((cmd) | (((idx) & 0x03) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SMBUS_ENCODE_RW(cmd, rw) ((cmd) | ((rw) & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SMBUS_BYTE_BLOCK_CMD_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SMBUS_GROUP_BLOCK_CMD_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Commands for read/write registers of Cypress trackpad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CYAPA_CMD_SOFT_RESET       0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CYAPA_CMD_POWER_MODE       0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CYAPA_CMD_DEV_STATUS       0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CYAPA_CMD_GROUP_DATA       0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CYAPA_CMD_GROUP_CMD        0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CYAPA_CMD_GROUP_QUERY      0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CYAPA_CMD_BL_STATUS        0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CYAPA_CMD_BL_HEAD          0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CYAPA_CMD_BL_CMD           0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CYAPA_CMD_BL_DATA          0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CYAPA_CMD_BL_ALL           0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CYAPA_CMD_BLK_PRODUCT_ID   0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CYAPA_CMD_BLK_HEAD         0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CYAPA_CMD_MAX_BASELINE     0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CYAPA_CMD_MIN_BASELINE     0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BL_HEAD_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BL_DATA_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BL_STATUS_SIZE  3  /* Length of gen3 bootloader status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CYAPA_REG_MAP_SIZE  256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * Gen3 Operational Device Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * bit 7: Valid interrupt source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * bit 6 - 4: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * bit 3 - 2: Power status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * bit 1 - 0: Device status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define REG_OP_STATUS     0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define OP_STATUS_SRC     0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define OP_STATUS_POWER   0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define OP_STATUS_DEV     0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OP_STATUS_MASK (OP_STATUS_SRC | OP_STATUS_POWER | OP_STATUS_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * Operational Finger Count/Button Flags Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * bit 7 - 4: Number of touched finger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * bit 3: Valid data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * bit 2: Middle Physical Button
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * bit 1: Right Physical Button
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * bit 0: Left physical Button
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define REG_OP_DATA1       0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OP_DATA_VALID      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define OP_DATA_MIDDLE_BTN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define OP_DATA_RIGHT_BTN  0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define OP_DATA_LEFT_BTN   0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define OP_DATA_BTN_MASK (OP_DATA_MIDDLE_BTN | OP_DATA_RIGHT_BTN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			  OP_DATA_LEFT_BTN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * Write-only command file register used to issue commands and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * parameters to the bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * The default value read from it is always 0x00.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define REG_BL_FILE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define BL_FILE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * Bootloader Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * bit 7: Busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * bit 6 - 5: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * bit 4: Bootloader running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * bit 3 - 2: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * bit 1: Watchdog Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * bit 0: Checksum valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_BL_STATUS        0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BL_STATUS_REV_6_5    0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BL_STATUS_BUSY       0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BL_STATUS_RUNNING    0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BL_STATUS_REV_3_2    0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BL_STATUS_WATCHDOG   0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BL_STATUS_CSUM_VALID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BL_STATUS_REV_MASK (BL_STATUS_WATCHDOG | BL_STATUS_REV_3_2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			    BL_STATUS_REV_6_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * Bootloader Error Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * bit 7: Invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * bit 6: Invalid security key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * bit 5: Bootloading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * bit 4: Command checksum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * bit 3: Flash protection error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * bit 2: Flash checksum error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * bit 1 - 0: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define REG_BL_ERROR         0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BL_ERROR_INVALID     0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BL_ERROR_INVALID_KEY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BL_ERROR_BOOTLOADING 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BL_ERROR_CMD_CSUM    0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BL_ERROR_FLASH_PROT  0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BL_ERROR_FLASH_CSUM  0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BL_ERROR_RESERVED    0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BL_ERROR_NO_ERR_IDLE    0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BL_ERROR_NO_ERR_ACTIVE  (BL_ERROR_BOOTLOADING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CAPABILITY_BTN_SHIFT            3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CAPABILITY_LEFT_BTN_MASK	(0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CAPABILITY_RIGHT_BTN_MASK	(0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CAPABILITY_MIDDLE_BTN_MASK	(0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CAPABILITY_BTN_MASK  (CAPABILITY_LEFT_BTN_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			      CAPABILITY_RIGHT_BTN_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			      CAPABILITY_MIDDLE_BTN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PWR_MODE_MASK   0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PWR_MODE_FULL_ACTIVE (0x3f << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PWR_MODE_IDLE        (0x03 << 2) /* Default rt suspend scanrate: 30ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PWR_MODE_SLEEP       (0x05 << 2) /* Default suspend scanrate: 50ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PWR_MODE_BTN_ONLY    (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PWR_MODE_OFF         (0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PWR_STATUS_MASK      0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PWR_STATUS_ACTIVE    (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PWR_STATUS_IDLE      (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PWR_STATUS_BTN_ONLY  (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PWR_STATUS_OFF       (0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AUTOSUSPEND_DELAY   2000 /* unit : ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BTN_ONLY_MODE_NAME   "buttononly"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OFF_MODE_NAME        "off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Common macros for PIP interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PIP_HID_DESCRIPTOR_ADDR		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PIP_REPORT_DESCRIPTOR_ADDR	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PIP_INPUT_REPORT_ADDR		0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PIP_OUTPUT_REPORT_ADDR		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PIP_CMD_DATA_ADDR		0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PIP_RETRIEVE_DATA_STRUCTURE	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PIP_CMD_CALIBRATE		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PIP_BL_CMD_VERIFY_APP_INTEGRITY	0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PIP_BL_CMD_GET_BL_INFO		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PIP_BL_CMD_PROGRAM_VERIFY_ROW	0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PIP_BL_CMD_LAUNCH_APP		0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PIP_BL_CMD_INITIATE_BL		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PIP_INVALID_CMD			0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PIP_HID_DESCRIPTOR_SIZE		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PIP_HID_APP_REPORT_ID		0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PIP_HID_BL_REPORT_ID		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PIP_BL_CMD_REPORT_ID		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PIP_BL_RESP_REPORT_ID		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PIP_APP_CMD_REPORT_ID		0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PIP_APP_RESP_REPORT_ID		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PIP_READ_SYS_INFO_CMD_LENGTH	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PIP_BL_READ_APP_INFO_CMD_LENGTH	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PIP_MIN_BL_CMD_LENGTH		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PIP_MIN_BL_RESP_LENGTH		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PIP_MIN_APP_CMD_LENGTH		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PIP_MIN_APP_RESP_LENGTH		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PIP_UNSUPPORTED_CMD_RESP_LENGTH	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PIP_READ_SYS_INFO_RESP_LENGTH	71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PIP_BL_APP_INFO_RESP_LENGTH	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PIP_BL_GET_INFO_RESP_LENGTH	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PIP_BL_PLATFORM_VER_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PIP_BL_PLATFORM_VER_MASK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PIP_PRODUCT_FAMILY_MASK		0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PIP_PRODUCT_FAMILY_TRACKPAD	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PIP_DEEP_SLEEP_STATE_ON		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PIP_DEEP_SLEEP_STATE_OFF	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PIP_DEEP_SLEEP_STATE_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PIP_APP_DEEP_SLEEP_REPORT_ID	0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PIP_DEEP_SLEEP_RESP_LENGTH	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PIP_DEEP_SLEEP_OPCODE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PIP_DEEP_SLEEP_OPCODE_MASK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PIP_RESP_LENGTH_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define	    PIP_RESP_LENGTH_SIZE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PIP_RESP_REPORT_ID_OFFSET	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PIP_RESP_RSVD_OFFSET		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define     PIP_RESP_RSVD_KEY		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PIP_RESP_BL_SOP_OFFSET		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define     PIP_SOP_KEY			0x01  /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define     PIP_EOP_KEY			0x17  /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PIP_RESP_APP_CMD_OFFSET		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define     GET_PIP_CMD_CODE(reg)	((reg) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PIP_RESP_STATUS_OFFSET		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define VALID_CMD_RESP_HEADER(resp, cmd)				  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	(((resp)[PIP_RESP_REPORT_ID_OFFSET] == PIP_APP_RESP_REPORT_ID) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	((resp)[PIP_RESP_RSVD_OFFSET] == PIP_RESP_RSVD_KEY) &&		  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	(GET_PIP_CMD_CODE((resp)[PIP_RESP_APP_CMD_OFFSET]) == (cmd)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PIP_CMD_COMPLETE_SUCCESS(resp_data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	((resp_data)[PIP_RESP_STATUS_OFFSET] == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Variables to record latest gen5 trackpad power states. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define UNINIT_SLEEP_TIME	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define UNINIT_PWR_MODE		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PIP_DEV_SET_PWR_STATE(cyapa, s)		((cyapa)->dev_pwr_mode = (s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PIP_DEV_GET_PWR_STATE(cyapa)		((cyapa)->dev_pwr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PIP_DEV_SET_SLEEP_TIME(cyapa, t)	((cyapa)->dev_sleep_time = (t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PIP_DEV_GET_SLEEP_TIME(cyapa)		((cyapa)->dev_sleep_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PIP_DEV_UNINIT_SLEEP_TIME(cyapa)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		(((cyapa)->dev_sleep_time) == UNINIT_SLEEP_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* The touch.id is used as the MT slot id, thus max MT slot is 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CYAPA_MAX_MT_SLOTS  15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct cyapa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) typedef bool (*cb_sort)(struct cyapa *, u8 *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) enum cyapa_pm_stage {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	CYAPA_PM_DEACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	CYAPA_PM_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	CYAPA_PM_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	CYAPA_PM_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	CYAPA_PM_RUNTIME_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	CYAPA_PM_RUNTIME_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct cyapa_dev_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	int (*check_fw)(struct cyapa *, const struct firmware *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	int (*bl_enter)(struct cyapa *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int (*bl_activate)(struct cyapa *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int (*bl_initiate)(struct cyapa *, const struct firmware *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int (*update_fw)(struct cyapa *, const struct firmware *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	int (*bl_deactivate)(struct cyapa *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ssize_t (*show_baseline)(struct device *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			struct device_attribute *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ssize_t (*calibrate_store)(struct device *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			struct device_attribute *, const char *, size_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	int (*initialize)(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	int (*state_parse)(struct cyapa *cyapa, u8 *reg_status, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	int (*operational_check)(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int (*irq_handler)(struct cyapa *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	bool (*irq_cmd_handler)(struct cyapa *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int (*sort_empty_output_data)(struct cyapa *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			u8 *, int *, cb_sort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int (*set_power_mode)(struct cyapa *, u8, u16, enum cyapa_pm_stage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	int (*set_proximity)(struct cyapa *, bool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct cyapa_pip_cmd_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	struct mutex cmd_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct completion cmd_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	atomic_t cmd_issued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	u8 in_progress_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	bool is_irq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	cb_sort resp_sort_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	u8 *resp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int *resp_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	enum cyapa_pm_stage pm_stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct mutex pm_stage_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	u8 irq_cmd_buf[CYAPA_REG_MAP_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	u8 empty_buf[CYAPA_REG_MAP_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) union cyapa_cmd_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct cyapa_pip_cmd_states pip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum cyapa_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	CYAPA_STATE_NO_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	CYAPA_STATE_BL_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	CYAPA_STATE_BL_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	CYAPA_STATE_BL_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	CYAPA_STATE_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	CYAPA_STATE_GEN5_BL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	CYAPA_STATE_GEN5_APP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	CYAPA_STATE_GEN6_BL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	CYAPA_STATE_GEN6_APP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct gen6_interval_setting {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	u16 active_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	u16 lp1_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	u16 lp2_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* The main device structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct cyapa {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	enum cyapa_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	u8 status[BL_STATUS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	bool operational; /* true: ready for data reporting; false: not. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct regulator *vcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	char phys[32];	/* Device physical location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	bool irq_wake;  /* Irq wake is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	bool smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	/* power mode settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	u8 suspend_power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	u16 suspend_sleep_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	u8 runtime_suspend_power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	u16 runtime_suspend_sleep_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	u8 dev_pwr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	u16 dev_sleep_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct gen6_interval_setting gen6_interval_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	/* Read from query data region. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	char product_id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	u8 platform_ver;  /* Platform version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	u8 fw_maj_ver;  /* Firmware major version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	u8 fw_min_ver;  /* Firmware minor version. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	u8 btn_capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	u8 gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int max_abs_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	int max_abs_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	int physical_size_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	int physical_size_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	/* Used in ttsp and truetouch based trackpad devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	u8 x_origin;  /* X Axis Origin: 0 = left side; 1 = right side. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	u8 y_origin;  /* Y Axis Origin: 0 = top; 1 = bottom. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	int electrodes_x;  /* Number of electrodes on the X Axis*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	int electrodes_y;  /* Number of electrodes on the Y Axis*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	int electrodes_rx;  /* Number of Rx electrodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	int aligned_electrodes_rx;  /* 4 aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	int max_z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	 * Used to synchronize the access or update the device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	 * And since update firmware and read firmware image process will take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	 * quite long time, maybe more than 10 seconds, so use mutex_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	 * to sync and wait other interface and detecting are done or ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	struct mutex state_sync_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	const struct cyapa_dev_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	union cyapa_cmd_states cmd_states;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ssize_t cyapa_i2c_reg_read_block(struct cyapa *cyapa, u8 reg, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 				 u8 *values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ssize_t cyapa_smbus_read_block(struct cyapa *cyapa, u8 cmd, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			       u8 *values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ssize_t cyapa_read_block(struct cyapa *cyapa, u8 cmd_idx, u8 *values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int cyapa_poll_state(struct cyapa *cyapa, unsigned int timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 cyapa_sleep_time_to_pwr_cmd(u16 sleep_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u16 cyapa_pwr_cmd_to_sleep_time(u8 pwr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ssize_t cyapa_i2c_pip_read(struct cyapa *cyapa, u8 *buf, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ssize_t cyapa_i2c_pip_write(struct cyapa *cyapa, u8 *buf, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int cyapa_empty_pip_output_data(struct cyapa *cyapa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 				u8 *buf, int *len, cb_sort func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int cyapa_i2c_pip_cmd_irq_sync(struct cyapa *cyapa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			       u8 *cmd, int cmd_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			       u8 *resp_data, int *resp_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			       unsigned long timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			       cb_sort func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			       bool irq_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int cyapa_pip_state_parse(struct cyapa *cyapa, u8 *reg_data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bool cyapa_pip_sort_system_info_data(struct cyapa *cyapa, u8 *buf, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bool cyapa_sort_tsg_pip_bl_resp_data(struct cyapa *cyapa, u8 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int cyapa_pip_deep_sleep(struct cyapa *cyapa, u8 state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bool cyapa_sort_tsg_pip_app_resp_data(struct cyapa *cyapa, u8 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int cyapa_pip_bl_exit(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int cyapa_pip_bl_enter(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) bool cyapa_is_pip_bl_mode(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) bool cyapa_is_pip_app_mode(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int cyapa_pip_cmd_state_initialize(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int cyapa_pip_resume_scanning(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int cyapa_pip_suspend_scanning(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int cyapa_pip_check_fw(struct cyapa *cyapa, const struct firmware *fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int cyapa_pip_bl_initiate(struct cyapa *cyapa, const struct firmware *fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int cyapa_pip_do_fw_update(struct cyapa *cyapa, const struct firmware *fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int cyapa_pip_bl_activate(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int cyapa_pip_bl_deactivate(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ssize_t cyapa_pip_do_calibrate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			       struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			       const char *buf, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int cyapa_pip_set_proximity(struct cyapa *cyapa, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) bool cyapa_pip_irq_cmd_handler(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int cyapa_pip_irq_handler(struct cyapa *cyapa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) extern u8 pip_read_sys_info[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) extern u8 pip_bl_read_app_info[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) extern const char product_id[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) extern const struct cyapa_dev_ops cyapa_gen3_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) extern const struct cyapa_dev_ops cyapa_gen5_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) extern const struct cyapa_dev_ops cyapa_gen6_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #endif