Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PON_CNTL_1 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PON_CNTL_PULL_UP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PON_CNTL_TRIG_DELAY_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PON_CNTL_1_PULL_UP_EN			0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PON_CNTL_1_USB_PWR_EN			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PON_CNTL_1_WD_EN_RESET			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PM8058_SLEEP_CTRL			0x02b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PM8921_SLEEP_CTRL			0x10a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SLEEP_CTRL_SMPL_EN_RESET		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Regulator master enable addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_PM8058_VREG_EN_MSM			0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_PM8058_VREG_EN_GRP_5_4		0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Regulator control registers for shutdown/reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PM8058_S0_CTRL				0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PM8058_S1_CTRL				0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PM8058_S3_CTRL				0x111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PM8058_L21_CTRL				0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PM8058_L22_CTRL				0x121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PM8058_REGULATOR_ENABLE_MASK		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PM8058_REGULATOR_ENABLE			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PM8058_REGULATOR_DISABLE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PM8058_REGULATOR_PULL_DOWN_MASK		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PM8058_REGULATOR_PULL_DOWN_EN		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Buck CTRL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PM8058_SMPS_LEGACY_VREF_SEL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PM8058_SMPS_LEGACY_VPROG_MASK		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PM8058_SMPS_ADVANCED_BAND_MASK		0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PM8058_SMPS_ADVANCED_BAND_SHIFT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PM8058_SMPS_ADVANCED_VPROG_MASK		0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Buck TEST2 registers for shutdown/reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PM8058_S0_TEST2				0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PM8058_S1_TEST2				0x085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PM8058_S3_TEST2				0x11a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PM8058_REGULATOR_BANK_WRITE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PM8058_REGULATOR_BANK_MASK		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PM8058_REGULATOR_BANK_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PM8058_REGULATOR_BANK_SEL(n)	((n) << PM8058_REGULATOR_BANK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* Buck TEST2 register bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PM8058_SMPS_LEGACY_VLOW_SEL		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Buck TEST2 register bank 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PM8058_SMPS_ADVANCED_MODE_MASK		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PM8058_SMPS_ADVANCED_MODE		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PM8058_SMPS_LEGACY_MODE			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * @key_press_irq: key press irq number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * @regmap: device regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * @shutdown_fn: shutdown configuration function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) struct pmic8xxx_pwrkey {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int key_press_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int (*shutdown_fn)(struct pmic8xxx_pwrkey *, bool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static irqreturn_t pwrkey_press_irq(int irq, void *_pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct input_dev *pwr = _pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	input_report_key(pwr, KEY_POWER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	input_sync(pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static irqreturn_t pwrkey_release_irq(int irq, void *_pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct input_dev *pwr = _pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	input_report_key(pwr, KEY_POWER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	input_sync(pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int __maybe_unused pmic8xxx_pwrkey_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct pmic8xxx_pwrkey *pwrkey = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		enable_irq_wake(pwrkey->key_press_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int __maybe_unused pmic8xxx_pwrkey_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct pmic8xxx_pwrkey *pwrkey = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		disable_irq_wake(pwrkey->key_press_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static SIMPLE_DEV_PM_OPS(pm8xxx_pwr_key_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		pmic8xxx_pwrkey_suspend, pmic8xxx_pwrkey_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void pmic8xxx_pwrkey_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct pmic8xxx_pwrkey *pwrkey = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	bool reset = system_state == SYSTEM_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (pwrkey->shutdown_fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		error = pwrkey->shutdown_fn(pwrkey, reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * Select action to perform (reset or shutdown) when PS_HOLD goes low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 * Also ensure that KPD, CBL0, and CBL1 pull ups are enabled and that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 * USB charging is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	mask = PON_CNTL_1_PULL_UP_EN | PON_CNTL_1_USB_PWR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mask |= PON_CNTL_1_WD_EN_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		val &= ~PON_CNTL_1_WD_EN_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	regmap_update_bits(pwrkey->regmap, PON_CNTL_1, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * Set an SMPS regulator to be disabled in its CTRL register, but enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * in the master enable register.  Also set it's pull down enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * Take care to make sure that the output voltage doesn't change if switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * from advanced mode to legacy mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int pm8058_disable_smps_locally_set_pull_down(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u16 ctrl_addr, u16 test2_addr, u16 master_enable_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u8 master_enable_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u8 vref_sel, vlow_sel, band, vprog, bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	bank = PM8058_REGULATOR_BANK_SEL(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	error = regmap_write(regmap, test2_addr, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	error = regmap_read(regmap, test2_addr, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	reg &= PM8058_SMPS_ADVANCED_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* Check if in advanced mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (reg == PM8058_SMPS_ADVANCED_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		/* Determine current output voltage. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		error = regmap_read(regmap, ctrl_addr, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		band = reg & PM8058_SMPS_ADVANCED_BAND_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		band >>= PM8058_SMPS_ADVANCED_BAND_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		switch (band) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			vref_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			vlow_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			vref_sel = PM8058_SMPS_LEGACY_VREF_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			vlow_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			vref_sel = PM8058_SMPS_LEGACY_VREF_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			vlow_sel = PM8058_SMPS_LEGACY_VLOW_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			pr_err("%s: regulator already disabled\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		vprog = reg & PM8058_SMPS_ADVANCED_VPROG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		/* Round up if fine step is in use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		vprog = (vprog + 1) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		if (vprog > PM8058_SMPS_LEGACY_VPROG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			vprog = PM8058_SMPS_LEGACY_VPROG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		/* Set VLOW_SEL bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		bank = PM8058_REGULATOR_BANK_SEL(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		error = regmap_write(regmap, test2_addr, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		error = regmap_update_bits(regmap, test2_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			PM8058_REGULATOR_BANK_WRITE | PM8058_REGULATOR_BANK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				| PM8058_SMPS_LEGACY_VLOW_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			PM8058_REGULATOR_BANK_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			PM8058_REGULATOR_BANK_SEL(1) | vlow_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		/* Switch to legacy mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		bank = PM8058_REGULATOR_BANK_SEL(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		error = regmap_write(regmap, test2_addr, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		error = regmap_update_bits(regmap, test2_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				PM8058_REGULATOR_BANK_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				PM8058_REGULATOR_BANK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 				PM8058_SMPS_ADVANCED_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 				PM8058_REGULATOR_BANK_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				PM8058_REGULATOR_BANK_SEL(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				PM8058_SMPS_LEGACY_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		/* Enable locally, enable pull down, keep voltage the same. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		error = regmap_update_bits(regmap, ctrl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			PM8058_REGULATOR_ENABLE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			PM8058_REGULATOR_PULL_DOWN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			PM8058_SMPS_LEGACY_VREF_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			PM8058_SMPS_LEGACY_VPROG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			PM8058_REGULATOR_ENABLE | PM8058_REGULATOR_PULL_DOWN_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				| vref_sel | vprog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Enable in master control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	error = regmap_update_bits(regmap, master_enable_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			master_enable_bit, master_enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Disable locally and enable pull down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return regmap_update_bits(regmap, ctrl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int pm8058_disable_ldo_locally_set_pull_down(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		u16 ctrl_addr, u16 master_enable_addr, u8 master_enable_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	/* Enable LDO in master control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	error = regmap_update_bits(regmap, master_enable_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			master_enable_bit, master_enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* Disable LDO in CTRL register and set pull down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return regmap_update_bits(regmap, ctrl_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		PM8058_REGULATOR_ENABLE_MASK | PM8058_REGULATOR_PULL_DOWN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		PM8058_REGULATOR_DISABLE | PM8058_REGULATOR_PULL_DOWN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int pm8058_pwrkey_shutdown(struct pmic8xxx_pwrkey *pwrkey, bool reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct regmap *regmap = pwrkey->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* When shutting down, enable active pulldowns on important rails. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		/* Disable SMPS's 0,1,3 locally and set pulldown enable bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		pm8058_disable_smps_locally_set_pull_down(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			PM8058_S0_CTRL, PM8058_S0_TEST2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			REG_PM8058_VREG_EN_MSM, BIT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		pm8058_disable_smps_locally_set_pull_down(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			PM8058_S1_CTRL, PM8058_S1_TEST2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			REG_PM8058_VREG_EN_MSM, BIT(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		pm8058_disable_smps_locally_set_pull_down(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			PM8058_S3_CTRL, PM8058_S3_TEST2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			REG_PM8058_VREG_EN_GRP_5_4, BIT(7) | BIT(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		/* Disable LDO 21 locally and set pulldown enable bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		pm8058_disable_ldo_locally_set_pull_down(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			PM8058_L21_CTRL, REG_PM8058_VREG_EN_GRP_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			BIT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	 * Fix-up: Set regulator LDO22 to 1.225 V in high power mode. Leave its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	 * pull-down state intact. This ensures a safe shutdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	error = regmap_update_bits(regmap, PM8058_L22_CTRL, 0xbf, 0x93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/* Enable SMPL if resetting is desired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	mask = SLEEP_CTRL_SMPL_EN_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return regmap_update_bits(regmap, PM8058_SLEEP_CTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int pm8921_pwrkey_shutdown(struct pmic8xxx_pwrkey *pwrkey, bool reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct regmap *regmap = pwrkey->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	u8 mask = SLEEP_CTRL_SMPL_EN_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* Enable SMPL if resetting is desired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return regmap_update_bits(regmap, PM8921_SLEEP_CTRL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int pmic8xxx_pwrkey_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct input_dev *pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	int key_release_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	int key_press_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	unsigned int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	unsigned int pon_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct pmic8xxx_pwrkey *pwrkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	u32 kpd_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	bool pull_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (of_property_read_u32(pdev->dev.of_node, "debounce", &kpd_delay))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		kpd_delay = 15625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	/* Valid range of pwr key trigger delay is 1/64 sec to 2 seconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (kpd_delay > USEC_PER_SEC * 2 || kpd_delay < USEC_PER_SEC / 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		dev_err(&pdev->dev, "invalid power key trigger delay\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	pull_up = of_property_read_bool(pdev->dev.of_node, "pull-up");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (!regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		dev_err(&pdev->dev, "failed to locate regmap for the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	pwrkey = devm_kzalloc(&pdev->dev, sizeof(*pwrkey), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (!pwrkey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	pwrkey->shutdown_fn = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	pwrkey->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	pwrkey->key_press_irq = key_press_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	pwr = devm_input_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (!pwr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		dev_dbg(&pdev->dev, "Can't allocate power button\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	input_set_capability(pwr, EV_KEY, KEY_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	pwr->name = "pmic8xxx_pwrkey";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	pwr->phys = "pmic8xxx_pwrkey/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	delay = (kpd_delay << 6) / USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	delay = ilog2(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	err = regmap_read(regmap, PON_CNTL_1, &pon_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		dev_err(&pdev->dev, "failed reading PON_CNTL_1 err=%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pon_cntl &= ~PON_CNTL_TRIG_DELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	pon_cntl |= (delay & PON_CNTL_TRIG_DELAY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (pull_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		pon_cntl |= PON_CNTL_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		pon_cntl &= ~PON_CNTL_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	err = regmap_write(regmap, PON_CNTL_1, pon_cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		dev_err(&pdev->dev, "failed writing PON_CNTL_1 err=%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	err = devm_request_irq(&pdev->dev, key_press_irq, pwrkey_press_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			       IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			       "pmic8xxx_pwrkey_press", pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		dev_err(&pdev->dev, "Can't get %d IRQ for pwrkey: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			key_press_irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	err = devm_request_irq(&pdev->dev, key_release_irq, pwrkey_release_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			       IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			       "pmic8xxx_pwrkey_release", pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		dev_err(&pdev->dev, "Can't get %d IRQ for pwrkey: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			key_release_irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	err = input_register_device(pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		dev_err(&pdev->dev, "Can't register power key: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	platform_set_drvdata(pdev, pwrkey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct of_device_id pm8xxx_pwr_key_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	{ .compatible = "qcom,pm8058-pwrkey", .data = &pm8058_pwrkey_shutdown },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	{ .compatible = "qcom,pm8921-pwrkey", .data = &pm8921_pwrkey_shutdown },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_DEVICE_TABLE(of, pm8xxx_pwr_key_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct platform_driver pmic8xxx_pwrkey_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.probe		= pmic8xxx_pwrkey_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.shutdown	= pmic8xxx_pwrkey_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		.name	= "pm8xxx-pwrkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		.pm	= &pm8xxx_pwr_key_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.of_match_table = pm8xxx_pwr_key_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) module_platform_driver(pmic8xxx_pwrkey_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_ALIAS("platform:pmic8xxx_pwrkey");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_DESCRIPTION("PMIC8XXX Power Key driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_AUTHOR("Trilok Soni <tsoni@codeaurora.org>");