^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Freescale's 3-Axis Accelerometer MMA8450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MMA8450_DRV_NAME "mma8450"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MODE_CHANGE_DELAY_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define POLL_INTERVAL 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define POLL_INTERVAL_MAX 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MMA8450_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MMA8450_STATUS_ZXYDR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MMA8450_OUT_X8 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MMA8450_OUT_Y8 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MMA8450_OUT_Z8 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MMA8450_OUT_X_LSB 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MMA8450_OUT_X_MSB 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MMA8450_OUT_Y_LSB 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MMA8450_OUT_Y_MSB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MMA8450_OUT_Z_LSB 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MMA8450_OUT_Z_MSB 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MMA8450_XYZ_DATA_CFG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MMA8450_CTRL_REG1 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MMA8450_CTRL_REG2 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int mma8450_read(struct i2c_client *c, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = i2c_smbus_read_byte_data(c, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dev_err(&c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "failed to read register 0x%02x, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) off, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int mma8450_write(struct i2c_client *c, unsigned int off, u8 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) error = i2c_smbus_write_byte_data(c, off, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dev_err(&c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "failed to write to register 0x%02x, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) off, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int mma8450_read_block(struct i2c_client *c, unsigned int off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 *buf, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) err = i2c_smbus_read_i2c_block_data(c, off, size, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_err(&c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "failed to read block data at 0x%02x, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MMA8450_OUT_X_LSB, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void mma8450_poll(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct i2c_client *c = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int x, y, z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret = mma8450_read(c, MMA8450_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!(ret & MMA8450_STATUS_ZXYDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = mma8450_read_block(c, MMA8450_OUT_X_LSB, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) x = ((int)(s8)buf[1] << 4) | (buf[0] & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) y = ((int)(s8)buf[3] << 4) | (buf[2] & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) z = ((int)(s8)buf[5] << 4) | (buf[4] & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) input_report_abs(input, ABS_X, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) input_report_abs(input, ABS_Y, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) input_report_abs(input, ABS_Z, z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) input_sync(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Initialize the MMA8450 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int mma8450_open(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct i2c_client *c = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* enable all events from X/Y/Z, no FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) err = mma8450_write(c, MMA8450_XYZ_DATA_CFG, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Sleep mode poll rate - 50Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * System output data rate - 400Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Full scale selection - Active, +/- 2G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) err = mma8450_write(c, MMA8450_CTRL_REG1, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) msleep(MODE_CHANGE_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void mma8450_close(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct i2c_client *c = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mma8450_write(c, MMA8450_CTRL_REG1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mma8450_write(c, MMA8450_CTRL_REG2, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * I2C init/probing/exit functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int mma8450_probe(struct i2c_client *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) input = devm_input_allocate_device(&c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) input_set_drvdata(input, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) input->name = MMA8450_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) input->id.bustype = BUS_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) input->open = mma8450_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) input->close = mma8450_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) input_set_abs_params(input, ABS_X, -2048, 2047, 32, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) input_set_abs_params(input, ABS_Y, -2048, 2047, 32, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) input_set_abs_params(input, ABS_Z, -2048, 2047, 32, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) err = input_setup_polling(input, mma8450_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(&c->dev, "failed to set up polling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) input_set_poll_interval(input, POLL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) input_set_max_poll_interval(input, POLL_INTERVAL_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) err = input_register_device(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(&c->dev, "failed to register input device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct i2c_device_id mma8450_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { MMA8450_DRV_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MODULE_DEVICE_TABLE(i2c, mma8450_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct of_device_id mma8450_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "fsl,mma8450", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_DEVICE_TABLE(of, mma8450_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct i2c_driver mma8450_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .name = MMA8450_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .of_match_table = mma8450_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .probe = mma8450_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .id_table = mma8450_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) module_i2c_driver(mma8450_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_AUTHOR("Freescale Semiconductor, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_DESCRIPTION("MMA8450 3-Axis Accelerometer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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