^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * VTI CMA3000_D0x Accelerometer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Hemanth V <hemanthv@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/input/cma3000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "cma3000_d0x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CMA3000_WHOAMI 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CMA3000_REVID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CMA3000_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CMA3000_STATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CMA3000_RSTR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CMA3000_INTSTATUS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CMA3000_DOUTX 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CMA3000_DOUTY 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CMA3000_DOUTZ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CMA3000_MDTHR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CMA3000_MDFFTMR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMA3000_FFTHR 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMA3000_RANGE2G (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMA3000_RANGE8G (0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMA3000_BUSI2C (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMA3000_MODEMASK (7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMA3000_GRANGEMASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMA3000_STATUS_PERR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMA3000_INTSTATUS_FFDET (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Settling time delay in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMA3000_SETDELAY 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Delay for clearing interrupt in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CMA3000_INTDELAY 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Bit weights in mg for bit 0, other bits need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * multiply factor 2^n. Eight bit is the sign bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BIT_TO_2G 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BIT_TO_8G 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct cma3000_accl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct cma3000_bus_ops *bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct cma3000_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct input_dev *input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int bit_to_mg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int g_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CMA3000_READ(data, reg, msg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (data->bus_ops->read(data->dev, reg, msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CMA3000_SET(data, reg, val, msg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((data)->bus_ops->write(data->dev, reg, val, msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Conversion for each of the eight modes to g, depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * on G range i.e 2G or 8G. Some modes always operate in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 8G.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mode_to_mg[8][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { BIT_TO_8G, BIT_TO_2G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { BIT_TO_8G, BIT_TO_2G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { BIT_TO_8G, BIT_TO_8G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { BIT_TO_8G, BIT_TO_8G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { BIT_TO_8G, BIT_TO_2G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { BIT_TO_8G, BIT_TO_2G },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void decode_mg(struct cma3000_accl_data *data, int *datax,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int *datay, int *dataz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Data in 2's complement, convert to mg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *datax = ((s8)*datax) * data->bit_to_mg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *datay = ((s8)*datay) * data->bit_to_mg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *dataz = ((s8)*dataz) * data->bit_to_mg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static irqreturn_t cma3000_thread_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct cma3000_accl_data *data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int datax, datay, dataz, intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 ctrl, mode, range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) intr_status = CMA3000_READ(data, CMA3000_INTSTATUS, "interrupt status");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (intr_status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Check if free fall is detected, report immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (intr_status & CMA3000_INTSTATUS_FFDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) input_report_abs(data->input_dev, ABS_MISC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) input_sync(data->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) input_report_abs(data->input_dev, ABS_MISC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) datax = CMA3000_READ(data, CMA3000_DOUTX, "X");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) datay = CMA3000_READ(data, CMA3000_DOUTY, "Y");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dataz = CMA3000_READ(data, CMA3000_DOUTZ, "Z");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ctrl = CMA3000_READ(data, CMA3000_CTRL, "ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mode = (ctrl & CMA3000_MODEMASK) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) range = (ctrl & CMA3000_GRANGEMASK) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) data->bit_to_mg = mode_to_mg[mode][range];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Interrupt not for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (data->bit_to_mg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Decode register values to milli g */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) decode_mg(data, &datax, &datay, &dataz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) input_report_abs(data->input_dev, ABS_X, datax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) input_report_abs(data->input_dev, ABS_Y, datay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) input_report_abs(data->input_dev, ABS_Z, dataz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) input_sync(data->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int cma3000_reset(struct cma3000_accl_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Reset sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CMA3000_SET(data, CMA3000_RSTR, 0x02, "Reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CMA3000_SET(data, CMA3000_RSTR, 0x0A, "Reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CMA3000_SET(data, CMA3000_RSTR, 0x04, "Reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Settling time delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = CMA3000_READ(data, CMA3000_STATUS, "Status");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(data->dev, "Reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (val & CMA3000_STATUS_PERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(data->dev, "Parity Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int cma3000_poweron(struct cma3000_accl_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const struct cma3000_platform_data *pdata = data->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (data->g_range == CMARANGE_2G) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ctrl = (data->mode << 1) | CMA3000_RANGE2G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } else if (data->g_range == CMARANGE_8G) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ctrl = (data->mode << 1) | CMA3000_RANGE8G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_info(data->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "Invalid G range specified, assuming 8G\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ctrl = (data->mode << 1) | CMA3000_RANGE8G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ctrl |= data->bus_ops->ctrl_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CMA3000_SET(data, CMA3000_MDTHR, pdata->mdthr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "Motion Detect Threshold");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CMA3000_SET(data, CMA3000_MDFFTMR, pdata->mdfftmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "Time register");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CMA3000_SET(data, CMA3000_FFTHR, pdata->ffthr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "Free fall threshold");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = CMA3000_SET(data, CMA3000_CTRL, ctrl, "Mode setting");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) msleep(CMA3000_SETDELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int cma3000_poweroff(struct cma3000_accl_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = CMA3000_SET(data, CMA3000_CTRL, CMAMODE_POFF, "Mode setting");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) msleep(CMA3000_SETDELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int cma3000_open(struct input_dev *input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct cma3000_accl_data *data = input_get_drvdata(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!data->suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cma3000_poweron(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) data->opened = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void cma3000_close(struct input_dev *input_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct cma3000_accl_data *data = input_get_drvdata(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!data->suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cma3000_poweroff(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) data->opened = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void cma3000_suspend(struct cma3000_accl_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!data->suspended && data->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cma3000_poweroff(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) data->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EXPORT_SYMBOL(cma3000_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void cma3000_resume(struct cma3000_accl_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (data->suspended && data->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cma3000_poweron(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) data->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) EXPORT_SYMBOL(cma3000_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct cma3000_accl_data *cma3000_init(struct device *dev, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const struct cma3000_bus_ops *bops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const struct cma3000_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct cma3000_accl_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct input_dev *input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(dev, "platform data not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* if no IRQ return error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) data = kzalloc(sizeof(struct cma3000_accl_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) input_dev = input_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!data || !input_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) data->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) data->input_dev = input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data->bus_ops = bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) data->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) data->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mutex_init(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) data->mode = pdata->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (data->mode > CMAMODE_POFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) data->mode = CMAMODE_MOTDET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "Invalid mode specified, assuming Motion Detect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) data->g_range = pdata->g_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (data->g_range != CMARANGE_2G && data->g_range != CMARANGE_8G) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "Invalid G range specified, assuming 8G\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) data->g_range = CMARANGE_8G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) input_dev->name = "cma3000-accelerometer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) input_dev->id.bustype = bops->bustype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) input_dev->open = cma3000_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) input_dev->close = cma3000_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) __set_bit(EV_ABS, input_dev->evbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) input_set_abs_params(input_dev, ABS_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) -data->g_range, data->g_range, pdata->fuzz_x, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) input_set_abs_params(input_dev, ABS_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) -data->g_range, data->g_range, pdata->fuzz_y, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) input_set_abs_params(input_dev, ABS_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) -data->g_range, data->g_range, pdata->fuzz_z, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) input_set_abs_params(input_dev, ABS_MISC, 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) input_set_drvdata(input_dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) error = cma3000_reset(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rev = CMA3000_READ(data, CMA3000_REVID, "Revid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (rev < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) error = rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pr_info("CMA3000 Accelerometer: Revision %x\n", rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) error = request_threaded_irq(irq, NULL, cma3000_thread_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pdata->irqflags | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "cma3000_d0x", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(dev, "request_threaded_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) error = input_register_device(data->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(dev, "Unable to register input device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) free_irq(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) err_free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) input_free_device(input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return ERR_PTR(error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) EXPORT_SYMBOL(cma3000_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void cma3000_exit(struct cma3000_accl_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) free_irq(data->irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) input_unregister_device(data->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) EXPORT_SYMBOL(cma3000_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_DESCRIPTION("CMA3000-D0x Accelerometer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MODULE_AUTHOR("Hemanth V <hemanthv@ti.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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