^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011 Bosch Sensortec GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2011 Unixphere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This driver adds support for Bosch Sensortec's digital acceleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * sensors BMA150 and SMB380.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The SMB380 is fully compatible with BMA150 and only differs in packaging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The datasheet for the BMA150 chip can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * http://www.bosch-sensortec.com/content/language1/downloads/BST-BMA150-DS000-07.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bma150.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ABSMAX_ACC_VAL 0x01FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ABSMIN_ACC_VAL -(ABSMAX_ACC_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Each axis is represented by a 2-byte data word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BMA150_XYZ_DATA_SIZE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Input poll interval in milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BMA150_POLL_INTERVAL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BMA150_POLL_MAX 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BMA150_POLL_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BMA150_MODE_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BMA150_MODE_SLEEP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BMA150_MODE_WAKE_UP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Data register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BMA150_DATA_0_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BMA150_DATA_1_REG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BMA150_DATA_2_REG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Control register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BMA150_CTRL_0_REG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BMA150_CTRL_1_REG 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BMA150_CTRL_2_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BMA150_CTRL_3_REG 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Configuration/Setting register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BMA150_CFG_0_REG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BMA150_CFG_1_REG 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BMA150_CFG_2_REG 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BMA150_CFG_3_REG 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BMA150_CFG_4_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BMA150_CFG_5_REG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BMA150_CHIP_ID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BMA150_CHIP_ID_REG BMA150_DATA_0_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BMA150_ACC_X_LSB_REG BMA150_DATA_2_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BMA150_SLEEP_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BMA150_SLEEP_MSK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BMA150_SLEEP_REG BMA150_CTRL_0_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BMA150_BANDWIDTH_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BMA150_BANDWIDTH_MSK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BMA150_BANDWIDTH_REG BMA150_CTRL_2_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BMA150_RANGE_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BMA150_RANGE_MSK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BMA150_RANGE_REG BMA150_CTRL_2_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BMA150_WAKE_UP_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BMA150_WAKE_UP_MSK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BMA150_WAKE_UP_REG BMA150_CTRL_3_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BMA150_SW_RES_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BMA150_SW_RES_MSK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BMA150_SW_RES_REG BMA150_CTRL_0_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Any-motion interrupt register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BMA150_ANY_MOTION_EN_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BMA150_ANY_MOTION_EN_MSK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BMA150_ANY_MOTION_EN_REG BMA150_CTRL_1_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BMA150_ANY_MOTION_DUR_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BMA150_ANY_MOTION_DUR_MSK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BMA150_ANY_MOTION_DUR_REG BMA150_CFG_5_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BMA150_ANY_MOTION_THRES_REG BMA150_CFG_4_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Advanced interrupt register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BMA150_ADV_INT_EN_POS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BMA150_ADV_INT_EN_MSK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BMA150_ADV_INT_EN_REG BMA150_CTRL_3_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* High-G interrupt register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BMA150_HIGH_G_EN_POS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BMA150_HIGH_G_EN_MSK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BMA150_HIGH_G_EN_REG BMA150_CTRL_1_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BMA150_HIGH_G_HYST_POS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BMA150_HIGH_G_HYST_MSK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BMA150_HIGH_G_HYST_REG BMA150_CFG_5_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BMA150_HIGH_G_DUR_REG BMA150_CFG_3_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BMA150_HIGH_G_THRES_REG BMA150_CFG_2_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Low-G interrupt register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BMA150_LOW_G_EN_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BMA150_LOW_G_EN_MSK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BMA150_LOW_G_EN_REG BMA150_CTRL_1_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BMA150_LOW_G_HYST_POS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BMA150_LOW_G_HYST_MSK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BMA150_LOW_G_HYST_REG BMA150_CFG_5_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BMA150_LOW_G_DUR_REG BMA150_CFG_1_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BMA150_LOW_G_THRES_REG BMA150_CFG_0_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct bma150_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * The settings for the given range, bandwidth and interrupt features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * are stated and verified by Bosch Sensortec where they are configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * to provide a generic sensitivity performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct bma150_cfg default_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .any_motion_int = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .hg_int = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .lg_int = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .any_motion_dur = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .any_motion_thres = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .hg_hyst = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .hg_dur = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .hg_thres = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .lg_hyst = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .lg_dur = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .lg_thres = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .range = BMA150_RANGE_2G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .bandwidth = BMA150_BW_50HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int bma150_write_byte(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* As per specification, disable irq in between register writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) disable_irq_nosync(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enable_irq(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int bma150_set_reg_bits(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int val, int shift, u8 mask, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) data = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (data < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) data = (data & ~mask) | ((val << shift) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return bma150_write_byte(client, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int bma150_set_mode(struct bma150_data *bma150, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) error = bma150_set_reg_bits(bma150->client, mode, BMA150_WAKE_UP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) BMA150_WAKE_UP_MSK, BMA150_WAKE_UP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) error = bma150_set_reg_bits(bma150->client, mode, BMA150_SLEEP_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BMA150_SLEEP_MSK, BMA150_SLEEP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (mode == BMA150_MODE_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bma150->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int bma150_soft_reset(struct bma150_data *bma150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) error = bma150_set_reg_bits(bma150->client, 1, BMA150_SW_RES_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) BMA150_SW_RES_MSK, BMA150_SW_RES_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int bma150_set_range(struct bma150_data *bma150, u8 range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return bma150_set_reg_bits(bma150->client, range, BMA150_RANGE_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BMA150_RANGE_MSK, BMA150_RANGE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int bma150_set_bandwidth(struct bma150_data *bma150, u8 bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return bma150_set_reg_bits(bma150->client, bw, BMA150_BANDWIDTH_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) BMA150_BANDWIDTH_MSK, BMA150_BANDWIDTH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int bma150_set_low_g_interrupt(struct bma150_data *bma150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 enable, u8 hyst, u8 dur, u8 thres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) error = bma150_set_reg_bits(bma150->client, hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) BMA150_LOW_G_HYST_POS, BMA150_LOW_G_HYST_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) BMA150_LOW_G_HYST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) error = bma150_write_byte(bma150->client, BMA150_LOW_G_DUR_REG, dur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) error = bma150_write_byte(bma150->client, BMA150_LOW_G_THRES_REG, thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return bma150_set_reg_bits(bma150->client, !!enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) BMA150_LOW_G_EN_POS, BMA150_LOW_G_EN_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) BMA150_LOW_G_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int bma150_set_high_g_interrupt(struct bma150_data *bma150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 enable, u8 hyst, u8 dur, u8 thres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) error = bma150_set_reg_bits(bma150->client, hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) BMA150_HIGH_G_HYST_POS, BMA150_HIGH_G_HYST_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) BMA150_HIGH_G_HYST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) error = bma150_write_byte(bma150->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) BMA150_HIGH_G_DUR_REG, dur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) error = bma150_write_byte(bma150->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) BMA150_HIGH_G_THRES_REG, thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return bma150_set_reg_bits(bma150->client, !!enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) BMA150_HIGH_G_EN_POS, BMA150_HIGH_G_EN_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) BMA150_HIGH_G_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int bma150_set_any_motion_interrupt(struct bma150_data *bma150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 enable, u8 dur, u8 thres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) error = bma150_set_reg_bits(bma150->client, dur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) BMA150_ANY_MOTION_DUR_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) BMA150_ANY_MOTION_DUR_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) BMA150_ANY_MOTION_DUR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) error = bma150_write_byte(bma150->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) BMA150_ANY_MOTION_THRES_REG, thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) error = bma150_set_reg_bits(bma150->client, !!enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) BMA150_ADV_INT_EN_POS, BMA150_ADV_INT_EN_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) BMA150_ADV_INT_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return bma150_set_reg_bits(bma150->client, !!enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) BMA150_ANY_MOTION_EN_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) BMA150_ANY_MOTION_EN_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) BMA150_ANY_MOTION_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void bma150_report_xyz(struct bma150_data *bma150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 data[BMA150_XYZ_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) s16 x, y, z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = i2c_smbus_read_i2c_block_data(bma150->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) BMA150_ACC_X_LSB_REG, BMA150_XYZ_DATA_SIZE, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret != BMA150_XYZ_DATA_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) x = ((0xc0 & data[0]) >> 6) | (data[1] << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) y = ((0xc0 & data[2]) >> 6) | (data[3] << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) z = ((0xc0 & data[4]) >> 6) | (data[5] << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) x = sign_extend32(x, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) y = sign_extend32(y, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) z = sign_extend32(z, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) input_report_abs(bma150->input, ABS_X, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) input_report_abs(bma150->input, ABS_Y, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) input_report_abs(bma150->input, ABS_Z, z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) input_sync(bma150->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static irqreturn_t bma150_irq_thread(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) bma150_report_xyz(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void bma150_poll(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct bma150_data *bma150 = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bma150_report_xyz(bma150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int bma150_open(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct bma150_data *bma150 = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) error = pm_runtime_get_sync(&bma150->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (error < 0 && error != -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * See if runtime PM woke up the device. If runtime PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * is disabled we need to do it ourselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (bma150->mode != BMA150_MODE_NORMAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) error = bma150_set_mode(bma150, BMA150_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void bma150_close(struct input_dev *input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct bma150_data *bma150 = input_get_drvdata(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pm_runtime_put_sync(&bma150->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (bma150->mode != BMA150_MODE_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bma150_set_mode(bma150, BMA150_MODE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int bma150_initialize(struct bma150_data *bma150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) const struct bma150_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) error = bma150_soft_reset(bma150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) error = bma150_set_bandwidth(bma150, cfg->bandwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) error = bma150_set_range(bma150, cfg->range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (bma150->client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) error = bma150_set_any_motion_interrupt(bma150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) cfg->any_motion_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) cfg->any_motion_dur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) cfg->any_motion_thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) error = bma150_set_high_g_interrupt(bma150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cfg->hg_int, cfg->hg_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) cfg->hg_dur, cfg->hg_thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) error = bma150_set_low_g_interrupt(bma150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) cfg->lg_int, cfg->lg_hyst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cfg->lg_dur, cfg->lg_thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return bma150_set_mode(bma150, BMA150_MODE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int bma150_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) const struct bma150_platform_data *pdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) const struct bma150_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct bma150_data *bma150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct input_dev *idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(&client->dev, "i2c_check_functionality error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) chip_id = i2c_smbus_read_byte_data(client, BMA150_CHIP_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (chip_id != BMA150_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(&client->dev, "BMA150 chip id error: %d\n", chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) bma150 = devm_kzalloc(&client->dev, sizeof(*bma150), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!bma150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bma150->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (pdata->irq_gpio_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) error = pdata->irq_gpio_cfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "IRQ GPIO conf. error %d, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) client->irq, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cfg = &pdata->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cfg = &default_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) error = bma150_initialize(bma150, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) idev = devm_input_allocate_device(&bma150->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!idev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) input_set_drvdata(idev, bma150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) bma150->input = idev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) idev->name = BMA150_DRIVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) idev->phys = BMA150_DRIVER "/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) idev->id.bustype = BUS_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) idev->open = bma150_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) idev->close = bma150_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) input_set_abs_params(idev, ABS_X, ABSMIN_ACC_VAL, ABSMAX_ACC_VAL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) input_set_abs_params(idev, ABS_Y, ABSMIN_ACC_VAL, ABSMAX_ACC_VAL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) input_set_abs_params(idev, ABS_Z, ABSMIN_ACC_VAL, ABSMAX_ACC_VAL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (client->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) error = input_setup_polling(idev, bma150_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) input_set_poll_interval(idev, BMA150_POLL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) input_set_min_poll_interval(idev, BMA150_POLL_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) input_set_max_poll_interval(idev, BMA150_POLL_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) error = input_register_device(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) error = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) NULL, bma150_irq_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) BMA150_DRIVER, bma150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "irq request failed %d, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) client->irq, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) i2c_set_clientdata(client, bma150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int bma150_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int __maybe_unused bma150_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct bma150_data *bma150 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return bma150_set_mode(bma150, BMA150_MODE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int __maybe_unused bma150_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct bma150_data *bma150 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return bma150_set_mode(bma150, BMA150_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static UNIVERSAL_DEV_PM_OPS(bma150_pm, bma150_suspend, bma150_resume, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct i2c_device_id bma150_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { "bma150", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { "smb380", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { "bma023", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MODULE_DEVICE_TABLE(i2c, bma150_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static struct i2c_driver bma150_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .name = BMA150_DRIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .pm = &bma150_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .class = I2C_CLASS_HWMON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .id_table = bma150_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .probe = bma150_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .remove = bma150_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) module_i2c_driver(bma150_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_AUTHOR("Albert Zhang <xu.zhang@bosch-sensortec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_DESCRIPTION("BMA150 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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